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Applications of Hierarchical Verification in Model Checking

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Formal Methods in Computer-Aided Design (FMCAD 2000)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1954))

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Abstract

The LTL model checker that we use provides sound decomposition mechanisms within a purely model checking environment. We have exploited these mechanisms to successfully verify a wide spectrum of large and complex circuits. This paper describes a variety of the decomposition techniques that we have used as part of a large industrial formal verification effort on the Intel Pentium R 4 (Willamette) processor.

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Author information

Authors and Affiliations

  1. Performance Microprocessor Division, Intel Corporation, RA2-401, 5200 NE Elam Young Parkway, OR 97124, Hillsboro, USA

    Robert Beers, Rajnish Ghughal & Mark Aagaard

Authors
  1. Robert Beers
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  2. Rajnish Ghughal
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  3. Mark Aagaard
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Editor information

Editors and Affiliations

  1. Austin Research Laboratories, IBM Corporation, Mail Stop 9460, Building 904 11501 Burnet Road, 78758, Austin, Texas, USA

    Warren A. Hunt Jr.

  2. Computer Science Department, Indiana University, Lindley Hall, 150 W. Woodlawn Avenue, 47405-7104, Bloomington, Indiana, USA

    Steven D. Johnson

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© 2002 Springer-Verlag Berlin Heidelberg

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Beers, R., Ghughal, R., Aagaard, M. (2002). Applications of Hierarchical Verification in Model Checking. In: Hunt, W.A., Johnson, S.D. (eds) Formal Methods in Computer-Aided Design. FMCAD 2000. Lecture Notes in Computer Science, vol 1954. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-40922-X_1

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  • DOI: https://doi.org/10.1007/3-540-40922-X_1

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-41219-9

  • Online ISBN: 978-3-540-40922-9

  • eBook Packages: Springer Book Archive

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