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SAT-Based Verification without State Space Traversal

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Abstract

Binary Decision Diagrams (BDDs) have dominated the area of symbolic model checking for the past decade. Recently, the use of satisfiability (SAT) solvers has emerged as an interesting complement to BDDs. SAT-based methods are capable of coping with some of the systems that BDDs are unable to handle. The most challenging problem that has to be solved in order to adapt standard symbolic model checking to SAT-solvers is the boolean quanti fication necessary for traversing the state space. A possible approach to extending the applicability of SAT-based model checkers is therefore to reduce the amount of traversal. In this paper, we investigate a BDD-based verification algorithm due to van Eijk. Van Eijk’s algorithm tries to compute information that is sufficient to prove a given safety property directly. When this is not possible, the computed information can be used to reduce the amount of traversal needed by standard model checking algorithms. We convert van Eijk’s algorithm to use a SAT-solver instead of BDDs. We also make a number of improvements to the original algorithm, such as combining it with recently developed variants of induction. The result is a collection of substantially strengthened and complete verification methods that do not require state space traversal.

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© 2000 Springer-Verlag Berlin Heidelberg

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Bjesse, P., Claessen, K. (2000). SAT-Based Verification without State Space Traversal. In: Hunt, W.A., Johnson, S.D. (eds) Formal Methods in Computer-Aided Design. FMCAD 2000. Lecture Notes in Computer Science, vol 1954. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-40922-X_23

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  • DOI: https://doi.org/10.1007/3-540-40922-X_23

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-41219-9

  • Online ISBN: 978-3-540-40922-9

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