Abstract
Energy consumption is increasingly becoming an important metric in designing computing systems. This paper focuses on instruction scheduling algorithms to reduce energy. Our experimentation shows that the best scheduling from the performance perspective is not necessarily the best scheduling from the energy perspective. Further, scheduling techniques that consider both energy and performance simultaneously are found to be desirable. We also validate the energy estimates of the instruction schedules obtained using the energy transition cost tables by executing the instructions on a cycle-accurate energy simulator. We conclude the paper with a discussion of alternate ways of building energy transition tables and estimating absolute energy consumption.
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References
A. V. Aho, R. Sethi, and J. Ullman. Compilers: Principles, Techniques, and Tools. Addison-Wesley, 1986.
M. Kamble and K. Ghose. Analytical energy dissipation models for low power caches. In Proc. the International Symposium on Low Power Electronics and Design, p. 143, August 1997.
S. S. Muchnick. Advanced Compiler Design Implementation. Morgan Kaufmann Publishers, San Francisco, California, 1997.
A. Parikh, M. Kandemir, N. Vijaykrishnan and M. J. Irwin. Instruction Scheduling Based on Energy and Performance Constraints. In Proc. The IEEE CS Annual Workshop on VLSI, April 2000.
J. Russell. Assembly code power analysis of a high performance embedded processor family. Technical Report, Department of Electrical and Computer Engineering, University of Texas at Austin.
W.-T. Shiue and C. Chakrabarti. Memory exploration for low power, embedded systems. CLPE-TR-9-1999-20, Technical Report, Center for Low Power Electronics, Arizona State University, 1999.
V. Tiwari, S. Malik, A. Wolfe, and T. C. Lee. Instruction level power analysis and optimization of software. Journal of VLSI Signal Processing Systems, Vol. 13, No. 2, August 1996.
V. Tiwari, S. Malik, and A. Wolfe. Power analysis of embedded software: A first step towards software power minimization. IEEE Transactions on VLSI Systems, December 1994.
M. C. Toburen, T. M. Conte, and M. Reilly. Instruction scheduling for low power dissipation in high performance microprocessors. In Proc. the Power Driven Microarchitecture Workshop (ISCA’98), Barcelona, Spain, June 1998.
N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. Y. Kim, and W. Ye. Energydriven integrated hardware-software optimizations using SimplePower. In Proc. the International Symposium on Computer Architecture (ISCA’00), June 2000.
W. Ye. Architectural Level Power Estimation and Experimentation. Ph.D. Thesis, Comp. Sci. and Eng., The Pennsylvania State University, October 1999.
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© 2000 Springer-Verlag Berlin Heidelberg
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Parikh, A., Kandemir, M., Vijaykrishnan, N., Irwin, M.J. (2000). Energy-Aware Instruction Scheduling. In: Valero, M., Prasanna, V.K., Vajapeyam, S. (eds) High Performance Computing — HiPC 2000. HiPC 2000. Lecture Notes in Computer Science, vol 1970. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44467-X_30
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DOI: https://doi.org/10.1007/3-540-44467-X_30
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