Abstract
The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size that is fixed at design time. Miss rates for different applications can be improved if the line size could be adjusted dynamically at run time.We propose a system where the compiler can set the cache line size for different portions of the program and we show that the miss rate is greatly reduced as a result of this dynamic resizing.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Teresa L. Johnson and Wen mei Hwu. Run-time adaptive cache hierarchy management via reference analysis. In Proceedings of the 24th Annual International Symposium on Computer Architecture, 1997.
D. Sunada, D. Glasco, and M. Flynn. ABSS v2.0: SPARC simulator. Technical Report CSL-TR-98-755, Stanford University, 1998.
Jack E. Veenstra and Robert J. Fowler. Mint: A front end for efficient simulation of shared-memory multiprocessors. In Intl. Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, pages 201–207, 1994.
Alexander V. Veidenbaum, Weiyu Tang, Rajesh Gupta, Alexandru Nicolau, and Xiaomei Ji. Adapting cache line size to application behavior. In Proceedings ICS’99, June 1999.
Peter Van Vleet, Eric Anderson, Lindsay Brown, Jean-Loup Baer, and Anna Karlin. Pursuing the performance potential of dynamic cache line sizes. In Proceedings of 1999 International Conference on Computer Design, November 1999.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2001 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Nicolaescu, D., Ji, X., Veidenbaum, A., Nicolau, A., Gupta, R. (2001). Compiler-Directed Cache Line Size Adaptivity ⋆. In: Chong, F.T., Kozyrakis, C., Oskin, M. (eds) Intelligent Memory Systems. IMS 2000. Lecture Notes in Computer Science, vol 2107. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44570-6_15
Download citation
DOI: https://doi.org/10.1007/3-540-44570-6_15
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-42328-7
Online ISBN: 978-3-540-44570-8
eBook Packages: Springer Book Archive