Abstract
The performance gap between processor and memory is very serious problem in high performance computing because effective performance is limited by memory ability. In order to overcome this problem, we propose a new VLSI architecture called SCIMA which integrates software controllable memory into a processor chip in addition to ordinary data cache. Most of data access is regular in high performance computing. Software controllable memory is better at making good use of the regularity than conventional cache.
This paper presents its architecture and performance evaluation. In SCIMA, the ratio of software controllable memory and cache can be dynamically changed. Due to this feature, SCIMA is upper compatible with conventional memory architecture. Performance is evaluated by using CG and FT kernels of NPB Benchmark and a real application of QCD (Quantum ChromoDynamics). The evaluation results reveal that SCIMA is superior to conventional cache-based architecture. It is also revealed that the superiority of SCIMA increases when access latency of off-chip memory increases or its relative throughput gets lower.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
D. Burger, J. Goodman, and A. Kagi, “Memory Bandwidth Limitation of Future Microprocessor”, Proc. 23rd Int’l Symp. on Computer Architecture, pp.78–89, 1996
D. Callahan and A. Porterfield, “Data Cache Performance of Supercomputer Applications”, Proc. of Supercomputing’ 91, pp.564–572, 1990.
M. Lam, E. Rothberg and M. Wolf, “The cache performance and optimizations of Blocked Algorithms”, Proc. ASPLOS-IV, pp.63–74, 1991
S. Coleman and K.S. McKinley, “Tile size selection using cache organization and data layout”, Proc. of PLDI’95, pp.279–289, June 1995.
P. Panda, H. Nakamura, N. Dutt and A. Nicolau, “Augmenting Loop Tiling with Data Alignment for Improved Cache Performance”, IEEE Transactions on Computers, Vol 48,No. 2, pp.142–149, 1999
M. Kondo, H. Okawara, H. Nakamura, T. Boku and S. Sakai, “SCIMA: A Novel Processor Architecture for High Performance Computing”, Proc. of HPC-Asia 2000, pp.355–360, May 2000
D. Bailey, T. Harris, W. Saphir, R. Wijngaart, A. Woo, and M. Yarrow, “The NAS Parallel Benchmarks 2.0”, NASA Ames Research Center Report, NAS-05-020, 1995.
S. Aoki, R. Burkhalter, K. Kanaya, T. Yoshié, T. Boku, H. Nakamura, Y. Yamashita, “Performance of lattice QCD programs on CP-PACS”, Parallel Computing 25, pp.1243–1255, 1999
M. Kondo, H. Okawara, H. Nakamura, and T. Boku, “SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing”, ICCD-2000, pp.105–111, Oct. 2000
P. Ranganathan, S. Adve and N. Jouppi, “Reconfigurable Caches and their Application to Media Processing” Proc. 27th Int’l Symp. on Computer Architecture, pp.214–224, 2000
D. Chiou, P. Jain, S. Devadas, and L. Rudolph, “Application-Specific Memory Management for Embedded Systems Using Software-Controlled Caches”, Technical Report CGS-Memo 427, MIT, 1999
S. Agarwala, C. Fuoco, T. Anderson, and D. Comisky, “A multi-level memory system architecture for high-performance DSP applications”, ICCD-2000, pp.408–413, Oct. 2000
Sony’s emotionally charged chip. MICROPROCESSOR REPORT, Vol. 13,No. 5, 1999.
Strongarm speed to triple. MICROPROCESSOR REPORT, Vol. 13,No. 6, 1999.
K. Cooper and T. Harvey, “Compiler-controlled memory”, Proc. of ASPLOS-VIII, pp.2–11, 1998.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2001 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Nakamura, H., Kondo, M., Boku, T. (2001). Software Controlled Reconfigurable On-chip Memory for High Performance Computing. In: Chong, F.T., Kozyrakis, C., Oskin, M. (eds) Intelligent Memory Systems. IMS 2000. Lecture Notes in Computer Science, vol 2107. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44570-6_2
Download citation
DOI: https://doi.org/10.1007/3-540-44570-6_2
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-42328-7
Online ISBN: 978-3-540-44570-8
eBook Packages: Springer Book Archive