Abstract
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue queue for a superscalar processor that leverages transmission gate insertion to provide dynamic low-cost configurability of size and speed. A novel circuit structure dynamically gathers statistics of issue queue activity over intervals of instruction execution. These statistics are then used to change the size of an issue queue organization on-the-fly to improve issue queue energy and performance. When applied to a fixed, full-size issue queue structure, the result is up to a 70% reduction in energy dissipation. The complexity of the additional circuitry to achieve this result is almost negligible. Furthermore, self-timed techniques embedded in the adaptive scheme can provide a 56% decrease in cycle time of the CAM array read of the issue queue when we change the adaptive issue queue size from 32 entries (largest possible) to 8 entries (smallest possible in our design).
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© 2001 Springer-Verlag Berlin Heidelberg
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Buyuktosunoglu, A., Schuster, S., Brooks, D., Bose, P., Cook, P., Albonesi, D. (2001). An Adaptive Issue Queue for Reduced Power at High Performance. In: Falsafi, B., Vijaykumar, T.N. (eds) Power-Aware Computer Systems. PACS 2000. Lecture Notes in Computer Science, vol 2008. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44572-2_3
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DOI: https://doi.org/10.1007/3-540-44572-2_3
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