Abstract
In this paper we introduce our fault tolerant FPGA and explain the fault tolerant features of our FPGA. They result from the block structure, the cell structure, and the intrablock routing along with a global state machine for testing. The state machine along with comparator detects single stuck-at-zero/one faults in the cell structure and mask them on block level.
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References
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© 2000 Springer-Verlag Berlin Heidelberg
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Bartzick, T., Henze, M., Kickler, J., Woska, K. (2000). Design of a Fault Tolerant FPGA. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_16
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DOI: https://doi.org/10.1007/3-540-44614-1_16
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