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A Specific Test Methodology for Symmetric SRAM-Based FPGAs

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Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing (FPL 2000)

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Abstract

This paper describes a test methodology for symmetric SRAM-based FPGAs. From a fundamental point of view, a test methodology for FPGAs differs from the test methodology for ASICs mainly due to the configurability of such flexible devices. In the paper, the FPGA architecture is first analyzed identifying the test problems specific to FPGAs as well as the test properties. This architecture is divided into different architectural elements such as the logic cells, the interconnect cells and the RAM cells. For each architectural element appropriated fault models are proposed, and test configurations and test vectors are derived targeting the proposed fault models.

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References

  1. S.D. Brown, R.J. Francis, J. Rose, S.G. Vranesic, «Field-Programmable Gate Arrays», Kluwer Academic Publishers, 1992.

    Google Scholar 

  2. S.M. Trimberger (ed), «Field-Programmable Gate Array Technology», Kluwer Academic Publishers, 1994.

    Google Scholar 

  3. C. Jordan and W.P. Marnane, «Incoming Inspection of FPGAs», Proc. of IEEE European Test Conference, pp. 371–377, 1993.

    Google Scholar 

  4. M. Renovell, J. Figueras and Y. Zorian, «Testing the Interconnect Structure of Unconfigurated FPGA», IEEE European Test Workshop, pp. 125–129, Séte (Montpellier), FRANCE, June 1996

    Google Scholar 

  5. M. Renovell, J. Figueras and Y. Zorian, «Test of RAM-Based FPGA: Methodology and Application to the Interconnect», 15th IEEE VLSI Test Symposium, pp. 230–237, Monterey, CA, USA, May 1997.

    Google Scholar 

  6. M. Renovell, J.M. Portal, J. Figueras and Y. Zorian, «Test Pattern and Test Generation Methodology for the Logic of RAM-Based FPGA», IEEE Asian Test Symp., pp. 254–259, Akita, Japan, November, 1997.

    Google Scholar 

  7. M. Renovell, J.M. Portal, J. Figueras and Y. Zorian, «Testing the Configurable Logic of RAM-based FPGA», IEEE Int. Conf. on Design, Automation and Test in Europe, pp. 82–88, Paris, France, Feb 1998.

    Google Scholar 

  8. M. Renovell, J.M. Portal, J. Figueras and Y. Zorian, «Testing the Interconnect of RAM-Based FPGAs», IEEE Design & Test of Computer, Vol. 15, n∘1, pp. 45–50, January–March 1998.

    Article  Google Scholar 

  9. M. Renovell, J.M. Portal, J. Figueras and Y. Zorian, «SRAM-based FPGAs: Testing the RAM mode of the LUT/RAM modules», IEEE European Test Workshop, pp., 146–151, Barcelone, Spain, May 1998.

    Google Scholar 

  10. M. Renovell, J.M. Portal, J. Figueras and Y. Zorian, “Minimizing the Number of Test Configurations for different FPGA Families”, IEEE 8th Asian Test Symposium ATS99, pp. 363–368, Nov. 16–18, Shanghai, China, 1999.

    Google Scholar 

  11. M. Renovell, J.M. Portal, J. Figueras and Y. Zorian, «SRAM-Based FPGA: Testing the LUT/RAM modules», IEEE International Test Conference, pp. 1102–1111, Washington, DC, USA, Oct. 18–23, 1998.

    Google Scholar 

  12. M. Renovell, J.M. Portal, J. Figueras and Y. Zorian, “Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA’s”, IEEE Int. Conf. on Design, Automation and Test in Europe DATE99, pp. 618–622, March 10–12, Munich, Germany, 1999.

    Google Scholar 

  13. T. Inoue, H. Fujiwara, H. Michinishi, T. Yokohira and T. Okamoto, «Universal Test Complexity of Field-Programmable Gate Arrays», 4th Asian Test Symposium, pp. 259–265, Bangalora, November 1995, India.

    Google Scholar 

  14. H. Michinishi, T. Yokohira, T. Okamoto, T. Inoue, H. Fujiwara «A Test Methodology for Interconnect Structures of LUT-based FPGAs», IEEE 5th Asian Test Symposium, pp. 68–74, November 1996.

    Google Scholar 

  15. H. Michinishi, T. Yokohira, T. Okamoto, T. Inoue, H. Fujiwara «Testing for the Programming Circuits of LUT-based FPGAs», IEEE 6th Asian Test Symposium, pp. 242–247, November 1997.

    Google Scholar 

  16. T. Inoue, S. Miyazaki and H. Fujiwara«Universal Fault Diagnosis for Lookup Table FPGAs», IEEE Design & Test of Computer, special Issue on FPGAs, pp. 39–44, January–March 1998.

    Google Scholar 

  17. M. Abramovici and C. Stroud, «No-Overhead BIST for FPGAs», 1st IEEE International On-line Testing Workshop, pp. 90–92, Nice, FRANCE, 1995.

    Google Scholar 

  18. C. Stroud, P. Chen, S. Konala, M. Abramovici, «Evaluation of FPGA Ressources for Built-In Self Test of Programmable Logic Blocks», Proc. of 4th ACM/SIGDA Int. Symposium on FPGAs, pp. 107–113, 1996.

    Google Scholar 

  19. M. Abramovici, C. Stroud, «ILA BIST for FPGAs: A Free Lunch with Gourmet Food», 2nd IEEE International On-line Testing Workshop, pp. 91–95, Biarritz, FRANCE, 1996.

    Google Scholar 

  20. W.K. Huang and F. Lombardi, «An Approach for Testing Programmable/ Configurable Field Programmable Gate Arrays», 14th IEEE VLSI Test Symposium, pp. 450–455, Princeton, NJ, USA, May 1996.

    Google Scholar 

  21. F. Lombardi, D. Ashen, X.T. Chen, W.K. Huang «Diagnosing Programmable Interconnect Systems for FPGAs», FPGA‘96, pp. 100–106, Monterey CA, USA, 1996.

    Google Scholar 

  22. D.G. Ashen, F.J. Meyer, N. Park and F. Lombardi, «Testing of Programmable Logic Devices (PLD) with Faulty Resources», IEEE International Workshop on Defect & Tolerance in VLSI Systems, pp. 76–84, Paris, October 1997.

    Google Scholar 

  23. W.K. Huang, F.J. Meyer, N. Park and F. Lombardi, «Testing Memory Modules in SRAM-based Configurable FPGAs», IEEE International Workshop on Memory Technology, Design and Test, August, 1997.

    Google Scholar 

  24. M. Hermann and W. Hoffmann, «Fault modeling and test generation for FPGAs», in R.W. Hartenstein and M.Z. Servit (eds), Lecture Notes in Computer Science, Field Programmable Logic, Springer-Verlag, pp. 1–10, 1994.

    Google Scholar 

  25. Xilinx, «The Programmable Logic Data Book», San Jose, USA, 1994

    Google Scholar 

  26. W.H. Kautz, «Testing for Faults in Wiring Networks» IEEE Transactions on Computers, Vol. C-23, No. 4, pp. 358–363, 1974.

    Google Scholar 

  27. P. Goel and M.T. McMahon, «Electronic Chip-in Place Test» Proc. of International Test Conference, pp. 83–90, 1982.

    Google Scholar 

  28. N. Jarwala and C.W. Yau, «A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Networks» Proc. of International Test Conference, pp. 63–70, 1989.

    Google Scholar 

  29. M.S. Abadir and J.K. Reghbati, «Functional Testing of Semiconductor Random Access Memories», ACM Computing Surveys, 15(3), pp. 175–198, 1983.

    Article  Google Scholar 

  30. A.J. Van de Goor, Testing Semiconductor Memories: Theory and Practice, John Willey & Sons, 1991.

    Google Scholar 

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Author information

Authors and Affiliations

  1. Laboratoire d’Informatique, Robotique et Microélectronique de Montpellier, LIRMM-UM2, 161 Rue Ada, 34392, Montpellier, France

    M. Renovell

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  1. M. Renovell
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Editor information

Editors and Affiliations

  1. Computer Science Department, University of Kaiserslautern, P. O. Box. 30 49, 67653, Kaiserslautern, Germany

    Reiner W. Hartenstein

  2. Carinthia Tech Institute, Richard-Wagner-Str. 19, 9500, Villach, Austria

    Herbert Grünbacher

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© 2000 Springer-Verlag Berlin Heidelberg

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Renovell, M. (2000). A Specific Test Methodology for Symmetric SRAM-Based FPGAs. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_33

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  • DOI: https://doi.org/10.1007/3-540-44614-1_33

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67899-1

  • Online ISBN: 978-3-540-44614-9

  • eBook Packages: Springer Book Archive

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