Abstract
Multidimensional arrays are among the most common data types. Their use in configurable hardware requires the injective translation of the index tuple into a memory address. This problem is considered in the paper, searching for a balance between speed and waste of memory. The basic idea is to divide one of the index ranges such that one part is a power of two. In this way the indices can be concatenated with fewer loss. To combine both resulting parts into one memory, several techniques are used.
The integration of the proposed method into libraries and tools allows efficient description of algorithms on a higher abstraction level.
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Döring, A.C., Lustig, G. (2000). Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_67
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DOI: https://doi.org/10.1007/3-540-44614-1_67
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