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International Workshop on Field Programmable Logic and Applications

FPL 2000: Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing pp 729–738Cite as

Evaluation of Accelerator Designs for Subgraph Isomorphism Problem

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1896))

Abstract

Many applications can be modeled as subgraph isomorphism problems. However, this problem is generally NP-complete and difficult to compute. A custom computing circuit is a prospective solution for such problems. This paper examines various accelerator designs, and compares them quantitatively from two points of view: cost and performance. An algorithm that is suited for hardware implementation is also proposed. The hardware for the proposed algorithm is much smaller on logic scale, and operates at a higher frequency than Ullmann’s design. The prototype accelerator operates at 16.5MHz on a Lucent ORCA 2C15A, which outperforms the software implementation of Ullmann’s algorithm on a 400 MHz Pentium II.

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References

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Author information

Authors and Affiliations

  1. Department of Knowledge-based Information Engineering, Toyohashi University of Technology, Toyohashi, 441-8580, Japan

    Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangtham Udorn & Kouji Konishi

  2. Toshiba Corp., Japan

    Hidemitsu Saito

  3. Toyota Caelum Inc., Japan

    Lerdtanaseangtham Udorn

  4. NTT Software Corp., Japan

    Kouji Konishi

Authors
  1. Shuichi Ichikawa
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  2. Hidemitsu Saito
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  3. Lerdtanaseangtham Udorn
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  4. Kouji Konishi
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Editor information

Editors and Affiliations

  1. Computer Science Department, University of Kaiserslautern, P. O. Box. 30 49, 67653, Kaiserslautern, Germany

    Reiner W. Hartenstein

  2. Carinthia Tech Institute, Richard-Wagner-Str. 19, 9500, Villach, Austria

    Herbert Grünbacher

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© 2000 Springer-Verlag Berlin Heidelberg

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Ichikawa, S., Saito, H., Udorn, L., Konishi, K. (2000). Evaluation of Accelerator Designs for Subgraph Isomorphism Problem. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_77

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  • DOI: https://doi.org/10.1007/3-540-44614-1_77

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67899-1

  • Online ISBN: 978-3-540-44614-9

  • eBook Packages: Springer Book Archive

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