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The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware

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Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing (FPL 2000)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1896))

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Abstract

The paper explores a number of possible hardware architectures for implementing synchronous dataflow (SDF) models of digital signal processing (DSP) applications in reconfigurable logic components, for example, Field Programmable Gate Arrays (FPGAs). The objective is to produce efficient hardware implementations of SDF graphs by exploiting the parallelism inherent in most graphs whilst taking advantage of the reconfigurable aspects of the target architecture. Classic area/performance tradeoffs can be made in order to meet the requirements of DSP applications.

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Author information

Authors and Affiliations

  1. Department of Computation, UMIST, PO Box 88, Manchester, M60 1QD, UK

    Martyn Edwards & Peter Green

Authors
  1. Martyn Edwards
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  2. Peter Green
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Editor information

Editors and Affiliations

  1. Computer Science Department, University of Kaiserslautern, P. O. Box. 30 49, 67653, Kaiserslautern, Germany

    Reiner W. Hartenstein

  2. Carinthia Tech Institute, Richard-Wagner-Str. 19, 9500, Villach, Austria

    Herbert Grünbacher

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© 2000 Springer-Verlag Berlin Heidelberg

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Edwards, M., Green, P. (2000). The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_78

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  • DOI: https://doi.org/10.1007/3-540-44614-1_78

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67899-1

  • Online ISBN: 978-3-540-44614-9

  • eBook Packages: Springer Book Archive

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