Skip to main content

Formal Verification of a Reconfigurable Microprocessor

  • Conference paper
  • First Online:
Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing (FPL 2000)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1896))

Included in the following conference series:

  • 622 Accesses

Abstract

The increasing acceptance of reconfigurable logic in form of FPGAs or CPLDs has caused new research activities in the field of processor architecture, the reconfigurable processors. The basic idea consists in combining the flexibility of reconfigurable logic with the transparent and well-known instruction set programming model. In this way critical parts of the application can be implemented directly in hardware. It has been shown that reconfigurable microprocessors are able either to achieve speed-ups or to improve the cost/performance ratio for a broad range of applications [1].

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Rupp, C.R., Landguth, M., Garverick, T., Gomersall, E., Holt, H., Arnold, J.M., Gokhale, M.: The NAPA Adaptive Processing Architecture. In Proc. of FCCM’98, pp. 28–37, Napa, CA, 1998.

    Google Scholar 

  2. Barrett, C.W., Dill, D.L., Levitt, J.R.: Validity Checking for Combinations of Theories with Equality. In Proc. of FMCAD’96, Springer-Verlag, 1996.

    Google Scholar 

  3. Burch, J.R., Dill, D.L.: Automatic verification of pipelined microprocessors control, In Proc. of CAV’ 94, pp. 68–80, Stanford, CA, Springer-Verlag, 1994.

    Google Scholar 

  4. Sawitzki, S., Gratz, A., Spallek, R.G.: CoMPARE: A Simple Reconfigurable Processor Architecture Exploiting Instruction Level Parallelism. In Proc. of PART’98, pp. 213–224, Springer-Verlag, 1998.

    Google Scholar 

  5. Sawitzki, S., Spallek, R.G., Schönherr, J., Straube, B.: Formal Verification for Microprocessors with Extendable Instruction Set. In Proc. of ASAP 2000, IEEE, 2000.

    Google Scholar 

  6. Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach, 2nd ed., Morgan Kaufmann Publishers, San Francisco CA, 1996.

    MATH  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2000 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Sawitzki, S., Schönherr, J., Spallek, R.G., Straube, B. (2000). Formal Verification of a Reconfigurable Microprocessor. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_84

Download citation

  • DOI: https://doi.org/10.1007/3-540-44614-1_84

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67899-1

  • Online ISBN: 978-3-540-44614-9

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics