Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware

Abstract

In computer vision, images are often preprocessed by the so-called Gabor transform. Using a Gabor filter bank, an image can be decomposed into orientational components lying in a specified frequency range. This biologically motivated decomposition simplifies higher level image processing like extraction of contours or pattern recognition. However, the IEEE floating-point implementation of this filter is too slow for real-time image-processing, especially if mobile applications with limited resources are targeted. This paper describes how this can be overcome by a hardware-implementation of the filter algorithm.

The actual implementation is preceded by an analysis of the algorithm analyzing the effects of reduced-accuracy calculus and the possibility of parallelizing the process. The target device is a Xilinx Virtex FPGA which resides on a PCI rapid-prototyping board.