Abstract
We examine ways to increase product term usage efficiency and propose several new sharing architectures that addresses this problem. We also present a technology mapping algorithm for product term based FPGA embedded memory arrays. Our algorithm, pMapster, is used to investigate the effects of macrocell granularity and macrocell sharing on the amount of logic that can be packed into a product term embedded memory array.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Xilinx, Inc., XC4000E and XC4000X Field Programmable Gate Arrays Datasheet, ver. 1.6, May 1999.
Altera Corp., APEX20K Programmable Logic Device Family Datasheet, ver. 3.3, Jan. 2001.
Xilinx, Inc., Virtex-E 1.8V Field-Programmable Gate Arrays Datasheet, ver. 1.3, Feb. 2000.
Ngai, T., Rose, J., and Wilton, S. J. E., “An SRAM Programmable Field-Configurable Memory,” in Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, pp. 499–502, May 1995.
Wilton, S. J. E., “SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays”, in Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Feb. 1998.
Cong, J. and Xu, S., “Technology Mapping for FPGAs with Embedded Memory Blocks”, in Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Feb. 1998.
Heile, F. and Leaver, A., “Hybrid Product Term and LUT Based Architectures Using Embedded Memory Blocks”, in Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 13–16, Feb. 1999.
Anderson, J. H. and Brown, S. D., “Technology Mapping for Large Complex PLDs”, in Proceedings of the 35th ACM/IEEE Design Automation Conference, pp. 698–703, 1998.
Cong, J., Huang, H., and Yuan, X., “Technology Mapping for k/m-Macrocell Based FPGAs”, in Proceedings of the ACM/SIGDA International Symposium on Fireld-Programmable Gate Arrays, pp 51–59, Feb. 2000.
Krishnamoorthy, S., Swaminathan, S., and Tessier, R., “Area-Optimized Technology Mapping for Hybrid FPGAs,” in Proceedings of the International Conference on Field Programmable Logic and Applications, August 2000.
Heile, F., “Programmable Logic Array Device with Random Access Memory Configurable as Product Terms,” U.S. Patent No. 6020759, Feb. 2000.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2001 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Lin, E., Wilton, S.J.E. (2001). Macrocell Architectures for Product Term Embedded Memory Arrays. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_6
Download citation
DOI: https://doi.org/10.1007/3-540-44687-7_6
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-42499-4
Online ISBN: 978-3-540-44687-3
eBook Packages: Springer Book Archive