Design Space Exploration for Massively Parallel Processor Arrays

Abstract

In this paper, we describe an approach for the optimization of dedicated co-processors that are implemented either in hardware (ASIC) or configware (FPGA). Such massively parallel co-processors are typically part of a heterogeneous hardware/software-system. Each coprocessor is a massive parallel system consisting of an array of processing elements (PEs). In order to decide whether to map a computational intensive task into hardware, existing approaches either try to optimize for performance or for cost with the other objective being a secondary goal. Our approach presented here, instead, a) considers multiple objectives simultaneously. For a given specification, we explore space-time-mappings leading to different degrees of parallelism and cost, and different optimal hardware solutions. b) We show that the hardware cost may be efficiently determined in terms of the chosen space-time mapping by using state-of-the-art techniques in polyhedral theory. c) Finally, we introduce ideas to drastically reduce dimension and size of the search space of mapping candidates. d) The feasibility of our approach is shown for two realistic examples.

Supported in part by the German Science Foundation (DFG) Project SFB 376 “Massively Parallel Computation”.