Abstract
Energy dissipation is a critical concern for battery-powered embedded systems. Memory energy contributes significantly to overall energy in data intensive applications. Low power memory systems are being designed that support multiple power states of memory banks. In low power states, energy dissipation is reduced but time to access memory is increased. We abstract an energy model for the memory system and exploit it to develop algorithmic techniques for memory energy reduction. This is achieved by exploring the structure and data access pattern of a given algorithm to devise memory power management schedules. We illustrate our approach through two well-known embedded benchmarks — Matrix Multiplication and Fast Fourier Transform. The optimality of our schemes is discussed using information theoretic lower bounds on memory energy. Simulations demonstrate that significant energy reduction can be achieved by using our approach over state-of-the-art implementations.
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References
The AMRM project, http://www1.ics.uci.edu/amrm/.
T. Alexander and G. Kedem, “Distributed Prefetch-buffer/Cache Design for High Performance Memory systems,” Symposium on High-Performance Computer Architecture (HPCA), February 1996.
R. Athavale, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, “Influence of Array Allocation Mechanisms on Memory System Energy,” International Parallel and Distributed Processing Symposium (IPDPS), April 2001.
L. Benini, L. Macchiarulo, A. Macii, and M. Poncino, “Layout-Driven Memory Synthesis for Embedded Systems-on-Chip,” IEEE Transactions on VLSI Systems, Vol. 10(2), April 2002.
D. Burger, T. M. Austin, and S. Bennett, “The SimpleScalar Tool Set, Version 2.0,” Technical Report, UW-Madison, 1997.
F. Catthoor, K. Danckaert, S. Wuytack, and N. D. Dutt, “Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors,” IEEE Design & Test of Computers, Vol. 18(3), pp 70–82, May/June 2001.
R. Y. Chen and M. J. Irwin, “Architectural-Level Power Estimation and Design Experiments,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 6(1), pp 50–66, January 2001.
N. D. Dutt, “Memory Organization and Exploration for Embedded Systems-on-Silicon,” International Conference on VLSI and CAD (ICVC), October 1997.
X. Fan, C. Ellis, and A. R. Lebeck, “Memory Controller Policies for DRAM Power Management,” International Symposium on Low Power Electronics and Design (ISLPED), August 2001.
A. H. Farrahi, G. E. Tellez, and M. Sarrafzadeh, “Memory Segmentation to Exploit Sleep Mode Operation,” Design Automation Conference (DAC), June 1995.
FFTW, http://www.fft.org.
J. W. Hong and H. T. Kung, “I/O Complexity: The Red-Blue Pebble Game,” Symposium on Theory of Computing (STOC), May 1981.
P. Kirschenhofer, P. H. Prodinger, and W. Szpankowski, “On the balance property of patricia tries: External path length view,” Theoretical Computer Science, Vol. 68, pp 1–17, 1989.
P. M. Kogge, V. W. Freeh, K. Ghose, N. Toomarian, and N. Aranki, “Morph: Adding an Energy Gear to a High Performance Microarchitecture for Embedded Applications,” Kool Chips Workshop, MICRO-33, December 2000.
Intel PXA250 Processor, http://www.intel.com/design/pca/prodbref/298620.htm.
A. R. Lebeck, X. Fan, H. Zeng, and C. Ellis, “Power Aware Page Allocation,” International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), November 2000.
J. Luo and N. K. Jha, “Static and dynamic variable voltage scheduling algorithms for real-time heterogeneous distributed embedded systems,” International Conference on VLSI Design, Jan 2002.
T. V. Meeuwen, A. V. Zelst, F. Catthoor, “System-level Interconnect Architecture Exploration for Custom Memory Organzations,” International Symposium on Systems Synthesis (ISSS), October 2001.
Mibench version 1.0, http://eecs.umich.edu/jringenb/mibench.
EEMBC-Embedded Microprocessor Benchmarking Consortium, http://www.eembc.org.
“Mobile SDRAM Power Saving Features,” Technical Note TN-48-10, MICRON, http://www.micron.com.
L. Nachtergaele, F. Catthoor, and C. Kulkarni, “Random-Access Data Storage Components in Customized Architectures,” IEEE Design & Test of Computers, Vol. 18(3), pp 70–82, May/June 2001.
N. Park and V. K. Prasanna, “Cache Conscious Walsh-Hadamard Transform,” International Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 2001.
P. R. Panda, N. D. Dutt, A. Nicolau, F. Catthoor, A. Vandecapplelle, E. Brockmeyer, C. Kulkarni, and E. D. Greef, “Data Memory Organization and Optimizations in Application-Specific Systems,” IEEE Design & Test of Computers, Vol. 18(3), pp 56–68, May/June 2001.
PICO Radio, http://bwrc.eecs.berkeley.edu/Research/.
J. Pouwelse, K. Langendoen, and H. Sips, “Dynamic Voltage Scaling on a Low-Power Microprocessor,” UbiCom-Tech. Report, 2000.
Jan Rabaey, “Piconodes for Sensor Networks,” DARPA PACC PI Meeting, 2001.
S. Sen and S. Chatterjee, “Towards a Theory of Cache-Efficient Algorithms,” Symposium on Discrete Algorithms (SODA), January 2000.
W. T. Shiue and C. Chakrabarti, “Memory Exploration for Low Power Embedded Systems,” Design Automation Conference (DAC), October 1999.
A. Sinha and A. P. Chandrakasan, “JouleTrack — A WebB ased Tool for Software Energy Profiling,” Design Automation Conference (DAC), April 2001.
The SPIRAL Project, http://www.ece.cmu.edu/~spiral/.
W. Tang, A. V. Veidenbaum, and R. Gupta, “Architectural Adaptation for Power and Performance,” International Conference on ASIC, October 2001.
K. V. Palem, R. M. rabbah, V. J. Mooney III, P. Korlmaz, and K. Puttaswamy, “Power Optimization of Embedded Memory Systems via Data Remapping,” CREST Technical report, Georgia Institute of Technology, February 2002.
M. Singh and V. K. Prasanna, “Application Directed Power Management for Optimizing Memory Energy Dissipation,” Technical Report, EEB-Systems, University of Southern California, 2003.
M. A. Viredaz and D. A. Wallach, “Power Evaluation of a Handheld Computer: A Case Study,” COMPAQ WRL Research Report, January 2001.
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© 2003 Springer-Verlag Berlin Heidelberg
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Singh, M., Prasanna, V.K. (2003). Algorithmic Techniques for Memory Energy Reduction. In: Jansen, K., Margraf, M., Mastrolilli, M., Rolim, J.D.P. (eds) Experimental and Efficient Algorithms. WEA 2003. Lecture Notes in Computer Science, vol 2647. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44867-5_20
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DOI: https://doi.org/10.1007/3-540-44867-5_20
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