CMOS Implementation of Generalized Threshold Functions

Abstract

Threshold Logic (TL) gates can evaluate any linearly separable function via the computation of a weighted sum over the input variables. In this paper we generalize this mechanism and introduce the novel concept of k-order Generalized Threshold Logic (GTL) gates. Such a GTL gate has augmented computational capabilities as it can evaluate a weighted sum of k-term AND products over the input variables. Additionally, we propose an implementation scheme for second-order GTL gates in CMOS technology. To assess the practical implications of the augmented computational capabilities of GTL gates we present a one gate implementation of 2-input parity function and a scheme to compute the block carry-out function utilized in carry lookahead addition algorithms. Our results indicate that the k-order GTL gate based implementation of the carry-out for a k-bit block requires (k+1)² transistors in each data and threshold mapping bank as opposed to 3.2^k-1-2 transistors required by a standard TL gate based implementation.

All the operators are algebraic. In order to avoid confusion throughout the text, the Boolean And, Or, and Xor operators have designated the symbols, ^, _, and _ respectively.