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Review of Capacitive Threshold Gate Implementations

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Artificial Neural Networks and Neural Information Processing — ICANN/ICONIP 2003 (ICANN 2003, ICONIP 2003)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2714))

Abstract

This is an in-depth survey paper on capacitive hardware implementations of threshold logic gates. The different VLSI solutions include the switched capacitor and the floating gate and their variations. It will be shown how the distinct original proposals from both categories have evolved to become quite similar. The problems with this kind of implementations are pointed out, and their applications are discussed.

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References

  1. V. Beiu, J.M. Quintana and M.J. Avedillo: “VLSI Implementations of Threshold Logic: A Survey” accepted for publication at IEEE Trans. on Neural Networks special number on Hardware Implementations.

    Google Scholar 

  2. J. R. Burns, N.J. Trenton and R.A. Powlus, “Threshold circuit utilizing field effect transistors”, U.S: Patent 3 260 863, Jul. 12, 1966.

    Google Scholar 

  3. T. Shibata, and T. Ohmi, “A functional MOS transistor featuring gate-level weighted sum and threshold operations,” IEEE J. Solid-State Circuits, vol. SC-39, pp. 1444–1455, June 1992.

    Google Scholar 

  4. T. Shibata, “Intelligent VLSI Systems Based on a Psychological Brain Model”, Proceedings IEEE International Symposium on intelligent Signal Processing and Systems, pp. 323–332, November 2000.

    Google Scholar 

  5. T. Shibata, and T. Ohmi, “Neuron MOS binary-logic integrated circuits—Part I: Design fundamentals and soft-hardware-logic circuit implementation,” IEEE Trans. Electron Devices, vol. ED-40, pp. 570–576, Mar. 1993.

    Article  Google Scholar 

  6. T. Shibata, and T. Ohmi, “Neuron MOS binary-logic integrated circuits-Part II: Simplifying techniques of circuit configuration and their practical applications,” IEEE Trans. Electron Devices, vol. ED-40, pp. 974–979, May 1993.

    Article  Google Scholar 

  7. E. Rodríguez-Villegas, G. Huertas, M.J. Avedillo, J.M. Quintana, and A. Rueda, “A practical floating-gate Muller-C element using vMOS threshold gates,” IEEE Trans. Circuits Syst. II, vol. CAS2-48, pp. 102–106, Jan. 2001.

    Article  Google Scholar 

  8. H. Y. Kwon, K. Kotani, T. Shibata and T. Ohmi: “Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis”, IEICE Trans. Electron., Vol. E80-C, No. 7, pp. 924–929, Jul. 1997.

    Google Scholar 

  9. K. Kotani, T. Shibata, M. Imai, and T. Ohmi, “Clocked-neuron-MOS logic circuits employing auto-threshold-adjustment,” Proc. ISSCC’95, San Francisco (USA), 1995, pp. 320–321, 388

    Google Scholar 

  10. K. Kotani, T. Shibata, M. Imai, and T. Ohmi, “Clocked-controlled neuron-MOS logic gates,” IEEE Trans. Circuits Syst. II, vol. CAS2-45, pp. 518–522, Apr. 1998.

    Article  Google Scholar 

  11. R. Lashevsky, K. Takaara and M. Souma, “Neuron MOSFET as a way to design a hreshold gates with the threshold and input weigths alterable in real time”, Proc APCCAS’98, Chiangmai (Thailand), 1998, pp. 263–266.

    Google Scholar 

  12. W. Weber, S. Prange, R. Thewes, and E. Wohlrab, “A neuron MOS transistor-based multiplier cell,” in IEDM Technical Digest, 1995, pp. 21.5.1–21.5.4.

    Google Scholar 

  13. W. Weber, S.J. Prange, R. Thewes, E. Wohlrab, and A. Luck, “On the application of Neuron MOS transistor principle for modern VLSI design,” IEEE Trans. Electron Devices, vol. ED-43, pp. 1700–1708, Oct. 1996.

    Article  Google Scholar 

  14. H. Y. Huang, and T.N. Wang, “CMOS capacitor coupling logic (C 3 L) logic circuits,” Proc. Asia Pacific pp. 33–36 AP-ASIC, Cheju (Korea), 2000, pp. 33–36.

    Google Scholar 

  15. P. Celinski, J.F. López, S. Al-Sarawi, and D. Abbott, “Low power, high speed, charge recycling CMOS threshold logic gate,” Electron. Lett., vol. 37, no. 17, pp. 1067–1069, Aug. 2001.

    Article  Google Scholar 

  16. M. J. Avellido, J.M. Quintana, A. Rueda, and E. Jiménez, “A low-power CMOS threshold-gate,” Electron. Lett., vol. 31, pp. 2157–2159, Dec. 1995.

    Article  Google Scholar 

  17. P. Celinski. S. Al-Sarawi, D. Abbot, J.F. Lopez, “Low depth carry lookahead adder addition using charge recycling threshold logic,” Proc. ISCAS 2002, pp. 469–472, Scottsdale (USA).

    Google Scholar 

  18. P. Celinski, J.F. López, S. Al-Sarawi and D. Abbott, “Compact parallel (m, n) Counters based on Self-Timed Threshold Logic”, Electronics Letters, Vol. 38, No. 13, pp. 633–635, Jun 2002.

    Article  Google Scholar 

  19. Y. P. Tsividis, and D. Anastassiou, “Switched-capacitor neural networks,” Electron. Lett., vol. 23, pp. 958–959, mo. 1987.

    Article  Google Scholar 

  20. U. Çilingiroglu, “A purely capacitive synaptic matrix for fixed-weight neural networks,” IEEE Trans. Circuits Syst. II, vol. CAS2-38, pp. 210–217, Apr. 1991.

    Google Scholar 

  21. H. Özdemir, A. Kepkep, B. Pamir, Y. Leblebici, and U. Çilingiroglu, “A capacitive threshold-logic gate,” IEEE J. Solid-State Circuits, vol. SC-31, pp. 1141–1150, Aug. 1996.

    Article  Google Scholar 

  22. Y. Leblebici, F.K. Gürkaynak, and D. Mlynek, “A compact 31-input programmable majority gate based on capacitive threshold logic,” Proc. International Symposium on Circuits and Systems ISCAS’98, Monterey (USA), vol. 2, 1998, pp. 105–108.

    Google Scholar 

  23. A. Stokman, S. Cotofanã, and S. Vassiliadis, “A versatile threshold logic gate,” Proc. Annual Semiconductor Conference CAS’98, Sinaia, (Romania), 1998, pp. 163–166.

    Google Scholar 

  24. J. López Garcia, J. Fernandez Ramos, and A. Gago Bohórquez, “A balanced capacitive threshold logic gate,” Proc. Design of Circuits and Integrated Systems (DCIS’2000), Montpellier (France), 2000.

    Google Scholar 

  25. A. Luck, S. Jung, R. Brederlow, R. Thewes, K, Goser, and W. Weber, “On the design robustness of threshold logic gates using multi-input floating gate MOS transistors,” IEEE Trans. Electron Devices, vol. ED-47, pp. 1231–1240, Jun. 2000.

    Article  Google Scholar 

  26. S. Jung, R. Thewes, T. Scheiter, K.F. Goser, and W. Weber, “A low-power and high per formance CMOS fingerprint sensing and encoding architecture”, IEEE Journal of Solid State Circuits, Vol. 34, no. 7, pp. 978–984, Jul. 1999.

    Article  Google Scholar 

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Author information

Authors and Affiliations

  1. School of Electrical Engineer and Computer Science, Washington State University, Pullman, WA, 99164-2752, USA

    V. Beiu

  2. Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, Edificio CICA, Avda. Reina Mercedes s/n, 41012, Sevilla, Spain

    M. J. Avedillo & J. M. Quintana

Authors
  1. V. Beiu
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  2. M. J. Avedillo
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  3. J. M. Quintana
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Editor information

Editors and Affiliations

  1. Bogazici University, Bebek, 34342, Istanbul, Turkey

    Okyay Kaynak  & Ethem Alpaydin  & 

  2. Laboratory of Computer and Information Science, Helsinki University of Technology, P.O.B. 5400, 02015, Finland

    Erkki Oja

  3. Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong

    Lei Xu

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© 2003 Springer-Verlag Berlin Heidelberg

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Beiu, V., Avedillo, M.J., Quintana, J.M. (2003). Review of Capacitive Threshold Gate Implementations. In: Kaynak, O., Alpaydin, E., Oja, E., Xu, L. (eds) Artificial Neural Networks and Neural Information Processing — ICANN/ICONIP 2003. ICANN ICONIP 2003 2003. Lecture Notes in Computer Science, vol 2714. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44989-2_88

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  • DOI: https://doi.org/10.1007/3-540-44989-2_88

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-40408-8

  • Online ISBN: 978-3-540-44989-8

  • eBook Packages: Springer Book Archive

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