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On Proving Circuit Lower Bounds against the Polynomial-Time Hierarchy: Positive and Negative Results

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Computing and Combinatorics (COCOON 2003)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2697))

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Abstract

We consider the problem of proving circuit lower bounds against the polynomial-time hierarchy. We give both positive and negative results. For the positive side, for any fixed integer k > 0, we give an explicit Σ p2 language, acceptable by a Σ P2 -machine with running time \( O(n^{k^2 + k} ) \), that requires circuit size > n k. For the negative side, we propose a new stringent notion of relativization, and prove under this stringent relativization that every language in the polynomial-time hierarchy has polynomial circuit size. (For technical details, see also CW03.)

The first author is supported in part by NSF grants CCR-0208013 and CCR-0196197 and U.S.-Japan Collaborative Research NSF SBE-INT 9726724. The second author is supported in part by by the JSPS/NSF Collaborative Research 1999 and by the Ministry for Education, Grant-in-Aid for Scientific Research (C), 2001.

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Cai, JY., Watanabe, O. (2003). On Proving Circuit Lower Bounds against the Polynomial-Time Hierarchy: Positive and Negative Results. In: Warnow, T., Zhu, B. (eds) Computing and Combinatorics. COCOON 2003. Lecture Notes in Computer Science, vol 2697. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45071-8_22

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  • DOI: https://doi.org/10.1007/3-540-45071-8_22

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  • Print ISBN: 978-3-540-40534-4

  • Online ISBN: 978-3-540-45071-9

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