A Framework for Enhancing Code Quality in Limited Register Set Embedded Processors

Abstract

Spill code generated during register allocation greatly influences the overall quality of compiled code, both in terms of speed as well as size. In embedded systems, where size of memory is often a major constraint, the size of compiled code is very important. In this paper we present a framework for better generation and placement of spill code for RISC-style embedded processors. Our framework attempts to achieve efficient execution and reduce spill-induced code growth. Traditional graph-coloring allocators often make spilling decisions which are not guided by program structure or path-sensitive control flow information. Quite often, allocation decisions get heavily influenced by the choice of candidates for register residency. Especially for systems with a limited number of registers, if one is not careful to contain register pressure, it could lead to generation of a lot of spill code. We propose a framework which selectively demotes variables in a contained manner and influences the formation of live ranges. The decisions for selective demotion are made through a flow-analytic approach such that fewer spill instructions are generated. Our approach tries to keep variables as candidates for register allocation only along the paths where it is profitable to do so. We attempt to identify good local candidates for demotion, however, decisions are taken only after their global demotion costs are captured. We have implemented our framework inside the SGI MIPSPRO compiler. Our results show improvement over a Briggs-style allocator in reducing code size upto 3:5% and upto 8:2% in reducing static loads in some cases for a register set of size 8. The results are very encouraging for other parameters as well for various sizes of register sets.