Modular Exponentiation on Fine-Grained FPGA

Abstract

An efficient implementation of modular exponentiation is achieved by first designing a bit-level systolic array such that the whole procedure of modular exponentiation can be carried out without using global interconnections or memory to store intermediate results, and then mapping this design onto Xilinx XC6000 Field Programmable Gate Arrays. Taking as a starting point for a FPGA program an efficient bit-level systolic algorithm facilitates the design process but does not automatically guarantee the most efficient hardware solution. We use an example of modular exponentiation with Montgomery multiplication to demonstrate a role of layout optimisation and partitioning in mapping linear systolic arrays onto two-dimensional arrays of FPGA cells.