Abstract
Reduction of chip packaging and cooling costs for deep sub-micron System-On-Chip (SOC) designs is an emerging issue. We present a simulationbased methodology able to realistically model the complex environment in which a SOC design operates in order to provide early and accurate power consumption estimation. We show that a rich functional test bench provided by a designer with a deep knowledge of a complex system is very often not appropriate for power analysis and can lead to power estimation errors of some orders of magnitude. To address this issue, we propose an automatic input sequence generation approach based on a heuristic algorithm able to upgrade a set of test vectors provided by the designer. The obtained sequence closely reflects the worst-case power consumption for the chip and allows looking at how the chip is going to work over time.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
A. R. Chandrakasan, R. W. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, 1995
J. Rabaey, M. Pedram, Low Power Design Methodologies, Kluwer Academic Publishers, 1996
L. Benini, G. De Micheli, Dynamic Power Management: Design Techniques and CAD Tools, Kluwer Academic Publishers, 1997
J. Monteiro, S. Devadas, Computer-Aided Design techniques for Low Power Sequential Logic Circuits, Kluwer Academic Publishers, 1996
E. Macii, M. Pedram, F. Somenzi, High-level power modeling, estimation and optimization, Proc. Design Automation Conference, pp. 504–511, 1997
D. Kirkovski, M. Potkonjak, System-level synthesis of low-power hard real-time systems, Proc. Design Automation Conference, pp. 697–702, 1997
B. Dave, G. Lakshminarayana, N. H. Jha, COSYN: Hardware-software co-synthesis of embedded systems, Proc. Design Automation Conference, pp. 703–708, 1997
Y. Li, J. Henkel, A framework for estimating and minimizing energy dissipation of embedded HW/SW systems, Proc. Design Automation Conference, pp. 188–193, 1998
J. Henkel, A power hardware/software partitioning approach for core-based embedded systems, Proc. Design Automation Conference, pp. 122–127, 1999
M. Lajolo, L. Lavagno, A. Raghunathan, S. Dey, Efficient Power Co-estimation Techniques for System-on-Chip Design, Proc. Design Automation and Test in Europe, pp. 27–34, 2000
F. Balarin et al., Hardware-Software Co-design of Embedded Systems: The POLIS Approach, Kluwer Academic Publishers, 1997
H. Hsieh, A. Sangiovanni-Vincentelli, et al. Synchronous equivalence for embedded systems: a tool for design exploration, Proc. ICCAD 99.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2000 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Lajolo, M., Lavagno, L., Sonza Reorda, M., Violante, M. (2000). Early Power Estimation for System-on-Chip Designs. In: Soudris, D., Pirsch, P., Barke, E. (eds) Integrated Circuit Design. PATMOS 2000. Lecture Notes in Computer Science, vol 1918. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45373-3_11
Download citation
DOI: https://doi.org/10.1007/3-540-45373-3_11
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-41068-3
Online ISBN: 978-3-540-45373-4
eBook Packages: Springer Book Archive