An Adiabatic Multiplier

Abstract

Adiabatic switching might be a possibility to overcome the power losses in CMOS due to the charging of capacities. The design of adiabatic gates and registers has been examined in the past. The possibilities offered to the design of logic are evaluated in this paper.

For this purpose an array multiplier has been chosen as a representative for more complex structures. To provide the possibility of comparison, it has been realized as an adiabatic circuit as well as using a standard CMOS design. In this article special interest has been drawn to the placement of the registers in the adiabatic circuit. This was done by using a modified retiming algorithm.

Both designs were simulated using SPICE. Although the simulation results show a significant reduction of power, they have to be interpreted with caution. Based on them it is discussed whether the reduction of dissipated energy can compensate the required overhead or not.