Abstract
In this paper, a power management technique basedon dynamic frequency scaling is proposed. The proposed technique targets digital receivers employing adaptive sampling. Such circuits over-sample the analogue input signal, in order to succeed timing synchronization. The proposedtec hnique introduces power savings by forcing the receiver to operate only on the “correct” data for the time intervals during which synchronization is achieved. The simple architectural modifications, needed for the application of the proposed strategy, are described. As test-vehicle a number of FIR filters, which are the basic components of almost every digital receiver, are used. The experimental results prove that the application of the proposedtec hnique introduces significant power savings, while negligibly increasing area andcritical path.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Kluwer Academic Publishers, 1995.
L. Benini, G. De Micheli, DYNAMIC POWER MANAGEMENT: Design Techniques andCAD tools, Kluwer Academic Publishers, 1998.
L. Benini, P. Siegel, G. De Micheli, “Automatic Synthesis of Gated Clocks for Power Reduction in Sequential Circuits”, IEEE Design & Test of Computers, vol. 11, no. 4, pp. 32–40, 1994.
L. Benini, G. De Micheli, “Transformation and Synthesis of FSMs for Low Power Gated Clock Implementation”, IEEE Transaction on CAD, vol. 15, no. 6, pp. 630–643, 1996.
M. Aldina, J. Monteiro, S. Devadas, A. Ghosh, M. Papaefthymiou, “Precomputation-Based Sequential Logic Optimization for Low Power”, IEEE Tran. on VLSI Systems, vol. 2, no. 4, pp. 426–436, 1994.
V. Tiwari, S. Malik, P. Ashar, “Guarded Evaluation: Pushing Power Management in Logic Synthesis/Design”, Int’l Symposium on Low Power Design, pp. 221–226, Dana-Point, CA, April 1995.
K. Murota, K. Hirade, “GMSK Modulation for Digital Mobile Radio Telephony”, IEEE Transactions on Communications, Vol. Com 29, No 7, pp. 1044–1050, July, 1981.
E. Metaxakis, A. Tzimas and G. Kalivas, “A low complexity baseband receiver for direct conversion DECT-based portable communications”, in Proc of IEEE Int’l Conf. on Universal Personal Communications, pp. 45–49, Florence, Italy, 1998.
J. D. Gibson, The communications handbook, CRC Press and IEEE Press, 1997.
J. G. Proakis, Digital Communications, 3rd edition, McGraw-Hill, New York, NY 1995
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2000 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Zervas, N., Theoharis, S., Kakaroudas, A., Soudris, D., Theodoridis, G., Goutis, C. (2000). Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers. In: Soudris, D., Pirsch, P., Barke, E. (eds) Integrated Circuit Design. PATMOS 2000. Lecture Notes in Computer Science, vol 1918. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45373-3_6
Download citation
DOI: https://doi.org/10.1007/3-540-45373-3_6
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-41068-3
Online ISBN: 978-3-540-45373-4
eBook Packages: Springer Book Archive