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Hardware Support for Simulated Annealing and Tabu Search

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Parallel and Distributed Processing (IPDPS 2000)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1800))

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Abstract

In this paper, we present a concept of a CPU kernel with hardware support for local-search based optimization algorithms like Simulated Annealing (SA) and Tabu-Search (TS). The special hardware modules are(:i) A link ed-list memory representing the problem space. (ii) CPU instruction set extensions supporting fast moves within the neighborhood of a solution. (iii) Support for the generation of moves for both algorithms, SA and TS. (iv) A solution mover managing several solution memories according to the optimization progress. (v) Hardware addressing support for the calculation of cost functions. (vi) Support for nonlinear functions in the acceptance procedure of SA. (vii) A status module providing on-line information about the solution quality. (v) An acceptance prediction module supporting parallel SA algorithms. Simulations of a VHDL implementation show a speedup of up to 260 in comparison to an existing implementation without hardware support.

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References

  1. S Kirkpatrick, C D Gelatt, and M P Vecchi. Optimisation by simulated annealing. Science, 220:671–680, 1983.

    Article  MathSciNet  Google Scholar 

  2. Fred Glover. Tabu search: 1. ORSA Journal on Computing, 1(3):190–206, 1989.

    Article  Google Scholar 

  3. Fred Glover. Tabu search: 2. ORSA Journal on Computing, 2(1):4–32, 1990.

    Article  Google Scholar 

  4. K. W. Tindell, A. Burns, and A. J. Wellings. Allocating Hard Real-Time Tasks: An NP-Hard Problem Made Easy. The Journal of Real-Time Systems, (4):145–165, 1992.

    Article  Google Scholar 

  5. Jakob Axelsson. Architecture Synthesis an Partitioning of Real-Time Systems: A Comparison of Three Heuristic Search Strategies. In 5th International Workshop on Hardware/Software Codesign, pages 161–165, March, 24–26 1997.

    Google Scholar 

  6. E. Aarts and K. Lenstra. Local Search in Combinatorial Optimization. Interscience Series in Discrete Mathematics and Optimization. John Wiley & Sons, 1997.

    Google Scholar 

  7. Claudia Mathis, Martin Schmid and Reinhard Schneider. A Flexible Tool for Mapping and Scheduling Real-Time Applications on Parallel Systems. In Proceedings of the Third International Conference on Parallel Processing and Applied Mathematics, Kazimierz Dolny, Poland, September, 5–7 1999.

    Google Scholar 

  8. E. H. L. Aarts and J. H. M Korst. Simulated Annealing and Boltzmann Machines. Interscience Series in Discrete Mathematics and Optimization. John Wiley & Sons, Chichester, U.K., 1989.

    MATH  Google Scholar 

  9. Tarek M. Nabhan and Albert Y. Zomaya. Parallel simulated annealing algorithm with low communication overhead. IEEE Transactions on Parallel and Distributed Systems, 6(12): 1226–1233, December 1995.

    Article  Google Scholar 

  10. Soo-Young Lee and Kyung Geun Lee. Synchronous and asynchronous parallel simulated annealing with multiple Markov chains:. IEEE Transactions on Parallel and Distributed Systems, 7(10):993–1008, October 1996.

    Article  Google Scholar 

  11. Martin Schmid and Reinhard Schneider. A Model for Scheduling and Mapping DSP Applications onto Multi-DSP Platforms. In Proceedings of the International Conference on Signal Processing Applications and Technology. Miller Freeman, 1999.

    Google Scholar 

  12. David Abramson. A very high speed architecture for simulated annealing. j-COMPUTER, 25(5):27–36, May 1992.

    Google Scholar 

  13. J. Niittylahti. Simulated Annealing Hardware Tool. In The 2nd International Conference on Expert Systems for Development, pages 187–191, 1994.

    Google Scholar 

  14. Bang W. Lee and Bing J. Sheu. Paralleled hardware annealing for optimal solutions on electronic neural networks. IEEE Transactions on Neural Networks, 4(4):588–599, July 1993.

    Article  Google Scholar 

  15. B. Eschermann, O. Haberl, O. Bringmann, and O. Seitzr. COSIMA: A Self-Testable Simulated Annealing Processor for Universal Cost Functions. In EuroASIC, pages 374–377, Los Alamitos, CA, 1992. IEEE Computer Society Press.

    Google Scholar 

  16. Daniel R. Greening. Parallel Simulated Annealing Techniques. In In Emergent Computation, pages 293–306. MIT Press, Cambridge, MA, 1991.

    Google Scholar 

  17. A. Postula, D.A. Abramson, and P. Logothetis. A Tail of 2 by n Cities: Performing Combinatorial Optimization Using Linked Lists on Special Purpose Computers. In The International Conference on Computational Intelligence and Multimedia Applications (ICCIMA), Feb, 9–11 1998.

    Google Scholar 

  18. P.D. Hortensius, R.D. McLeod, and H.C. Card. “parallel random number generation for vlsi systems using cellular automata”. IEEE Transactions on Computers, 38(10):1466–1473, October 1989.

    Article  Google Scholar 

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© 2000 Springer-Verlag Berlin Heidelberg

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Schneider, R., Weiss, R. (2000). Hardware Support for Simulated Annealing and Tabu Search. In: Rolim, J. (eds) Parallel and Distributed Processing. IPDPS 2000. Lecture Notes in Computer Science, vol 1800. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45591-4_89

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  • DOI: https://doi.org/10.1007/3-540-45591-4_89

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67442-9

  • Online ISBN: 978-3-540-45591-2

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