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Formal Verification Methods for Industrial Hardware Design

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2234))

Abstract

Functional validation of hardware designs is a major challenge for circuit design companies. Post-delivery software problems can be addressed by subsequent software releases; however, fixing hardware bugs in any shipped product is expensive. Simulation remains the dominate functional validation method, but in the last decade, formal verification (FV) has emerged as an important complementary method. We describe basic FV methods: theorem proving, model checking, and equivalence checking with some illustrations from their applications to Alpha microprocessor designs. The last one is described in detail. Although theoretically, FV can provide much more complete verification coverage than simulation, our ability to apply FV is limited due to capacity limits of existing FV tools and the availability of trained personnel. The application of FV to industrial designs is an active research area with huge opportunities for academic and industrial researchers.

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© 2001 Springer-Verlag Berlin Heidelberg

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Slobodová, A. (2001). Formal Verification Methods for Industrial Hardware Design. In: Pacholski, L., Ružička, P. (eds) SOFSEM 2001: Theory and Practice of Informatics. SOFSEM 2001. Lecture Notes in Computer Science, vol 2234. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45627-9_10

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  • DOI: https://doi.org/10.1007/3-540-45627-9_10

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