Abstract
The current paper presents a new algorithm and two architectures for the power-sum operation (AB 2 + C) over GF(2m) using a standard basis. The proposed algorithm is based on the MSB-first scheme and the proposed architectures have a low hardware complexity and small latency compared to conventional approaches. In particular, the hardware complexity and latency of the proposed parallel-in parallel-out array are about 19.8% and 25% lower, respectively, than Wei’s. In addition, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI implementation and can be easily applied to inverse/division architecture.
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© 2002 Springer-Verlag Berlin Heidelberg
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Kim, NY., Lee, WH., Yoo, KY. (2002). Efficient Power-Sum Systolic Architectures for Public-Key Cryptosystems in GF(2m). In: Ibarra, O.H., Zhang, L. (eds) Computing and Combinatorics. COCOON 2002. Lecture Notes in Computer Science, vol 2387. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45655-4_18
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DOI: https://doi.org/10.1007/3-540-45655-4_18
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