Abstract
Dual supply voltage scaling (DSVS) is an emerging technique in logic-level power optimization. In this paper, a novel design methodology, which enables DSVS to be carried out in a state-of-the-art environment for power-driven logic synthesis, is presented. The idea is to provide a dual supply voltage standard cell library modeled such that a typical gate sizing algorithm can be exploited for DSVS. Since this approach renders dedicated DSVS algorithms superfluous, only little modification of established design flows is required. The methodology has been applied to MCNC benchmark circuits. Compared to the results of single supply voltage power-driven logic synthesis, additional power reductions of 10% on average and 24% in the best case have been achieved.
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© 2002 Springer-Verlag Berlin Heidelberg
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Mahnke, T., Stechele, W., Hoeld, W. (2002). Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_15
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DOI: https://doi.org/10.1007/3-540-45716-X_15
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