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Trends in Ultralow-Voltage RAM Technology

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2451))

Abstract

This paper describes ultralow-voltage RAM technology for standalone and embedded memories in terms of signal-to-noise-ratio designs of RAM cells and subthreshold-current reduction. First, structures and areas of current DRAM and SRAM cells are discussed. Next, low-voltage peripheral circuits that have been proposed so far are reviewed with focus on subthreshold-current reduction, speed variation, on-chip voltage conversion, and testing. Finally, based on the above discussion, a perspective is given with emphasis on needs for high-speed simple non-volatile RAMs, new devices/circuits for reducing active- mode leakage currents, and memory-rich SOC architectures.

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© 2002 Springer-Verlag Berlin Heidelberg

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Itoh, K. (2002). Trends in Ultralow-Voltage RAM Technology. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_30

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  • DOI: https://doi.org/10.1007/3-540-45716-X_30

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-44143-4

  • Online ISBN: 978-3-540-45716-9

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