Abstract
The Multi-process DSP architecture (MDSP) is presented and evaluated for high-performance low-power embedded processors. The proposed architecture extends the standard control-flow DSP architecture with simple data-flow primitives. Such primitives are used to generate concurrent processes at run-time, which independently generate and consume data without accessing the instruction flow. We have evaluated the MDSP proposal by designing an asynchronous DSP core, since previous studies showed it to be better suited as an implementation technique. The experiment showed interesting improvements in overall performance and external device management compared to the current commercially available DSP cores. It also showed good scalability and compiler-friendliness with respect to alternative approaches.
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© 2002 Springer-Verlag Berlin Heidelberg
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Pessolano, F., Kessels, J., Peeters, A. (2002). MDSP: A High-Performance Low-Power DSP Architecture. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_4
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DOI: https://doi.org/10.1007/3-540-45716-X_4
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