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International Workshop on Power and Timing Modeling, Optimization and Simulation

PATMOS 2002: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation pp 429–437Cite as

Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2451))

Abstract

In this paper, an analytical delay model of Source-Coupled Logic (SCL) gates is proposed. In particular, the multiplexer, the XOR and the D-latch gates are considered. The method starts from a linearization of SCL gates, and analysis of the equivalent circuit obtained is simplified by introducing the dominant-pole approximation. The delay expression obtained is quite simple and each term has an evident circuit meaning, hence it is useful to design. The model was validated by extensive comparison with Spectre simulations by using a 0.35-μm CMOS technology. Results show that the predicted delay values agree well with simulated results.

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Author information

Authors and Affiliations

  1. DII— Dipartimento di Ingegneria dell’Informazione, Università di Siena, v. Roma n. 56, I-53100, Siena, Italy

    M. Alioto

  2. DEES— Dipartimento Elettrico Elettronico e Sistemistico, Universita’ di Catania, viale Andrea Doria 6, I-95125, CATANIA, ITALY

    G. Palumbo

Authors
  1. M. Alioto
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  2. G. Palumbo
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Editor information

Editors and Affiliations

  1. Ecole d’Ingénieurs du Canton de Vaud Microelectronics and Systems Institute, Digital Communications Team, Swiss University of Applied Science, Rue de Galilée 15, 1400, Yverdon, Switzerland

    Bertrand Hochet

  2. Instituto de Microelectrónica de Sevilla-CNM-CSIC Departamento do Diseño Digital Departamento de Electrónica y Electromagnetismo Departamento de Tecnología Electrónica, Universidad de Sevilla, Avda. Reina Mercedes, s/n. Edif. CICA

    Antonio J. Acosta  & Manuel J. Bellido  & 

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© 2002 Springer-Verlag Berlin Heidelberg

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Alioto, M., Palumbo, G. (2002). Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_43

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  • DOI: https://doi.org/10.1007/3-540-45716-X_43

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-44143-4

  • Online ISBN: 978-3-540-45716-9

  • eBook Packages: Springer Book Archive

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