Abstract
This paper discusses architectural solutions that deal with the high data throughput and the high computational power—two crucial performance requirements of MPEG standards. To increase the data throughput, we define a new data storage facility with a specific data organization and a new addressing mode. More specifically, we introduce an addressing function and refer to it as two-dimensional block addressing. Furthermore, we propose such an addressing approach, as an architectural feature and we believe it has useful properties that may position it as a basic addressing mode in future multimedia architectures. In addition, we propose an instruction set extension, utilizing the advantages of this addressing mode, as means of improving the computational power of a general-purpose super-scalar processor. To illustrate this concept, we have implemented a new instruction “ACcepted Quality” as a dedicated systolic structure. This instruction supports the corresponding function “ACQ” as defined in the Verification Model of MPEG-4. Its FPGA realization suggests 62 ns operating latency. Utilizing this result, we have made performance evaluations with a benchmark software (MPEG-4 shape encoder) using a cycle-accurate simulator. The simulation results indicate that the performance is increased by up to 10%. The introduced approach can be utilized by data encoding tools, which are based on block division of data. These tools are an essential part of many recent and up coming visual data compression standards like MPEG-4.
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Kuzmanov, G., Vassiliadis, S., van Eijndhoven, J.T.J. (2002). A 2D Addressing Mode for Multimedia Applications. In: Deprettere, E.F., Teich, J., Vassiliadis, S. (eds) Embedded Processor Design Challenges. SAMOS 2001. Lecture Notes in Computer Science, vol 2268. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45874-3_17
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DOI: https://doi.org/10.1007/3-540-45874-3_17
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