Abstract
This paper presents and analyzes a methodology for improving the quality of results in Field Programmable Gate Arrays (FPGAs) by taking advantage of the design hierarchy. We use a representative case study, which is a real design, to demonstrate how taking advantage of the hierarchy may lead to higher area-efficiency and better speed-performance. According to our results, an area saving of 18% along with a speedup of 15% is achievable; these area and speed improvements may result in a cost saving of a factor of two for volume production. Our analysis also shows that the above savings will not have a negative impact on routability and power consumption.
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© 2002 Springer-Verlag Berlin Heidelberg
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Kaviani, A.S. (2002). Using Design Hierarchy to Improve Quality of Results in FPGAs. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_104
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DOI: https://doi.org/10.1007/3-540-46117-5_104
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