Abstract
Although methods for watermarking Field Programmable Gate Arrays (FPGA) have been proposed, they require a high-level design approach whereby additional circuitry, or information embedded in unused logic elements indicate design ownership. The method proposed in this paper is unique in that: it is applied directly to the bit-stream used to configure Look Up Table (LUT) -based FPGAs; has no effect on the operation of the device; can be applied retrospectively to existing designs; attacks require both detailed knowledge of device architecture and direct manipulation of the design at a bitstream level.
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Carline, D., Coulton, P. (2002). A Novel Watermarking Technique for LUT Based FPGA Designs. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_129
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DOI: https://doi.org/10.1007/3-540-46117-5_129
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