Abstract
Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task.
In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility.
This work is partially supported by the Swiss National Science Foundation (SNF) under the NCCR MICS.
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References
G. Brebner and O. Diessel. Chip-Based Reconfigurable Task Management. In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL), pages 182–191, 2001.
O. Corp. RTEMS Homepage. http://www.rtems.com.
M. Dyer and M. Wirz. Reconfigurable System on FPGA. Master’s thesis, Computer Engineering and Networks Lab, ETH Zurich, March 2002.
J. Gaisler. LECCS: LEON/ERC32 Cross Compilation System. http://www.gaisler.com/leccs.html.
J. Gaisler. The LEON Processor User’s Manual. Gaisler Research, version 2.3.7 edition, August 2001.
S. A. Guccione, D. Levi, and P. Sundararajan. JBits: A Java-based Interface for Reconfigurable Computing. In Proceedings of the 2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), 2000.
A. Haase. Untersuchungen zur dynamischen Rekonfigurierbarkeit von FPGA. Master’s thesis, TU Chemnitz-Zwickau, Germany, September 2001. (in German).
E. L. Horta and J. W. Lockwood. PARBIT: A Tool to Transform Bitfiles to Implement Partial Recon.guration of Field Programmable Gate Arrays (FPGAs). Technical report, Department of Computer Science, Applied Research Lab, Washington University, Saint Louis, July 2001.
P. James-Roxby, E. Cerro-Prada, and S. Charlwood. A Core-based Design Method for Reconfigurable Computing Applications. In Proceedings of the IEE Colloquium on Reconfigurable Systems, Glasgow, March 1999. IEE Informatics.
D. Lampret. OpenRISC 1200 IP Core specification. http://www.opencores.org, 2001.
P. Leong, C. Sham, W. Wong, W. Yuen, and M. Leong. A Bitstream Reconfigurable FPGA Implementation of the WSAT Algorithm. IEEE Transactions on VLSI Systems, 9(1):197–201, February 2001.
S. Singh and P. James-Roxby. Lava and JBits: From HDL to Bitstream in Seconds. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), 2001.
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Dyer, M., Plessl, C., Platzner, M. (2002). Partially Reconfigurable Cores for Xilinx Virtex. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_31
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DOI: https://doi.org/10.1007/3-540-46117-5_31
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