Abstract
This paper describes a method for customising the representation of floating-point numbers that exploits the flexibility of reconfigurable hardware. The method determines the appropriate size of mantissa and exponent for each operation in a design, so that a cost function with a given error specification for the output relative to a reference representation can be satisfied. We adopt an iterative implementation of this method, which supports IEEE single-precision or double-precision floating-point representation as the reference representation. This implementation produces customised floating-point formats with arbitrarysized mantissa and exponent. The tool follows a generic framework designed to cover a variety of arithmetic representations and their hardware implementations; both combinational and pipelined designs can be developed. Results show that, particularly for calculations involving large dynamic ranges, our tool can produce hardware that is smaller and faster when compared with a design adopting the reference representation.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Benedetti, A. and Perona, P., “Bit-width optimisation for configurable DSP’s by multi-interval analysis”, Proc. Signals, Systems and Computers, IEEE, 2000.
Bondalapati, K. and Prasanna, V.K., “Dynamic precision management for loop computations on reconfigurable architectures”, Proc. FCCM, IEEE, 1999.
Budiu, M. et. al. “BitValue inference: detecting and exploiting narrow bitwidth compilations”, Proc. EuroPar Conf., 2000.
Celoxica Limited, http://www.celoxica.com.
Constantinides, G.A., Cheung, P.Y.K. and Luk, W., “The multiple wordlength paradigm”, Proc. FCCM, IEEE, 2001.
Hwang, J., Milne, B., Shirazi, N. and Stroomer, D., “System level tools for DSP in FPGAs”, Proc. FPL, LNCS 2147, Springer, 2001.
Jaenicke, A. and Luk, W., “Parameterised floating-point arithmetic on FPGAs”, Proc. Acoustics, Speech, and Signal Processing, IEEE, 2001.
Kim, S., Kum, K. and Sung, S., “Fixed point optimization utility for C and C++ based digital signal programs”, IEEE Trans. on Circuits and Systems II, 1998.
Kum, K.I. and Sung, W., “Combined word-length Optimization and high-level synthesis of digital signal processing systems”, IEEE Trans. on CAD, Aug. 2001.
Leong, M.P. et. al., “Automatic floating to fixed point translation and its application to post-rendering 3D warping”, Proc. FCCM, IEEE, 1999.
Lethje, O. et. al., ”A novel approach to code analysis of digital signal processors”, Proc. Compilers, Architecture, and Synthesis for Embedded Systems, ACM, 2001.
Luk, W. and McKeever, S., “Pebble: a language for parametrised and reconfigurable hardware design”, FPL, LNCS 1482, Springer, 1998.
Luo, Z. and Martonosi, M. “Accelerating pipelined integer nt accumulations in configurable hardware with delayed addition techniques”, IEEE Trans. on Computers, Vol. 49, No. 3, 2000.
Shirazi, N., Walters, A. and Athanas, P. “Quantitative analysis of floating-point arithmetic on FPGA based custom computing machines”, Proc. FCCM, IEEE, 1995.
Stephenson, M., Babb, J. and Amarasinghe, S., “Bitwidth analysis with application to silicon compilation”, Proc. Prog. Language Design and Imple., ACM, 2000.
Yap, C. and Dube, T., “The exact computation paradigm”, Computing in Euclidean Geometry, 2nd Ed., World Scientific Press, 1995.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Gaffar, A.A., Luk, W., Cheung, P.Y., Shirazi, N., Hwang, J. (2002). Automating Customisation of Floating-Point Designs. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_55
Download citation
DOI: https://doi.org/10.1007/3-540-46117-5_55
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-44108-3
Online ISBN: 978-3-540-46117-3
eBook Packages: Springer Book Archive