Abstract
The capabilities of general-purpose workstations are commonly enhanced by the addition of application-specific coprocessors located on the system expansion bus or a dedicated local bus. In order to determine the limits of applicability of such systems, performance estimation tools are required which are capable both of generating accurate predictions and supporting rapid evaluation of architectural alternatives. This paper describes a performance estimation method which meets these requirements. By combining data acquired using a variety of established techniques, and integrating these using a novel approach designed to capture far more of the intrinsic complexity of the system, extremely accurate estimates of performance can be generated. A detailed uncertainty analysis is provided, and the method is evaluated by comparing an application running on a coprocessor-enhanced workstation with model-based predictions, demonstrating estimation accuracy to be within ±5% of measured values.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Y. Yamaguchi, A. Miyashita, T. Maruyama, T. Hoshino, “A Co-processor System with a Virtex FPGA for Evolutionary Computation”, Proc. 10 th Intl. Workshop on Field Programmable Logic and Applications, FPL.00, LNCS#1896, Springer-Verlag (2000)
K. Leung, K. Ma, W. Wong, P. Leong, “FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor”, Proc. 8 th Intl. Symposium on FPGAs for Custom Computing Machines, FCCM’00, pp. 68–76, IEEE Computer Society (2000)
B. Carrión-Schäfer, S. Quigley, A. Chan, “Analysis and Implementation of the Discrete Element Method using a Dedicated Highly Parallel Architecture in Reconfigurable Computing”, to appear in Proc. 10 th Intl. Symposium on FPGAs for Custom Computing Machines, FCCM’02, IEEE Computer Society (2002)
S. Sudhir, N. Suman, S. Goldstein, “Configuration Caching and Swapping”, Proc. 11 th Intl. Workshop on Field Programmable Logic and Applications, FPL’01, LNCS#2147, pp. 192–202, Springer-Verlag (2001)
S. Singh, S. Slous, “Accelerating Adobe Photoshop with Reconfigurable Logic”, Proc. 6 th Intl. Symposium on FPGAs for Custom Computing Machines, FCCM’98, IEEE Computer Society (1998)
M. Dao, T. Cook, D. Silver, P. D. Urbano, “Acceleration of Template-Based Ray Casting for Volume Visualisation using FPGAs”, 3 rd Intl. Symposium on FPGAs for Custom Computing Machines, FCCM’95, pp. 116–123, IEEE Computer Society (1995)
S. Charlwood, J. Mangnall, S. Quigley, “Model-Based Performance Analysis for Reconfigurable Coprocessors”, in “Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications”, Proc. of SPIE Vol. 4525, SPIE (2001)
K. Chatha, R. Vemuri, “Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns”, Proc. 9 th Intl. Workshop on Rapid System Prototyping, RSP’98, IEEE Computer Society (1998)
K. Bondalapati, “Modeling and Mapping for Dynamically Reconfigurable Hybrid Architectures”, PhD Thesis, University of Southern California (2001)
D. Kerbyson, E. Papeafstathiou, J. Harper, S. Perry, G. Nudd, “Is Predictive Tracing Too Late for HPC Users?”, High Performance Computing, Plenum Press (1998)
Y. Li, S. Malik, “Performance Analysis of Embedded Software Using Implicit Path Enumeration”, Proc. 32 nd ACM/IEEE Design Automation Conference, DAC’95 (1995)
S.-S. Lim, Y. Bae, G., Jang, et al. “An Accurate Worst-Case Timing Analysis for RISC Processors”, IEEE Transactions on Software Engineering, Vol. 21, No. 7, IEEE (1995)
T. Hey, A. Dunlop, E. Hernández, “Realistic Parallel Performance Estimation”, Parallel Computing, Vol. 23, pp. 5–21 (1997)
K. Bondalapati, V. Prasanna, “DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems”, Proc. 9 th Intl. Workshop on Field Programmable Logic and Applications, FPL’99, LNCS#1673, Springer-Verlag (1999)
J. Walrath, R. Vemuri, “A Performance Modeling and Analysis Environment for Reconfigurable Computers”, Proc. Reconfigurable Architectures Workshop, RAW’98, LNCS#1388, Springer-Verlag (1998)
R. Hartenstein, M. Herz., T. Hoffman, U. Nageldinger, “On Reconfigurable Co-Processing Units”, Proc. Reconfigurable Architectures Workshop, RAW’98, LNCS#1388, Springer-Verlag (1998)
P. Bevington, D. Robinson, “Data Reduction and Error Analysis for the Physical Sciences”, 2nd Edition, McGraw-Hill (1994)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Charlwood, S., Mangnall, J., Quigley, S. (2002). System-Level Modelling for Performance Estimation of Reconfigurable Coprocessors. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_59
Download citation
DOI: https://doi.org/10.1007/3-540-46117-5_59
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-44108-3
Online ISBN: 978-3-540-46117-3
eBook Packages: Springer Book Archive