Abstract
For a Reconfigurable Computing device the wordlength - the size of the basic unit of data transported by the routing network and operated on by the processing elements - is a key parameter. This paper shows that wordlengths around 4 or 5 represent a “sweet spot” that optimizes the fraction of the silicon area that is used for processing rather than routing.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Marshall, Stansfield, Kostarnov, Vuillemin & Hutchings “A Reconfigurable Arithmetic Array for Multimedia Applications” in FPGA 99 proceedings
Rose, Francis, Lewis & Chow “Architecture of Field-Programmable Gate Arrays: The effect of Logic Block Functionality on Area Efficiency” JSSC Oct. 1990 pp. 1217–1225
A DeHon, “Reconfigurable Architectures for General-Purpose Computing”, MIT, Artificial Intelligence Laboratory, AI Technical Report No. 1586, 1996.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Stansfield, T. (2002). Wordlength as an Architectural Parameter for Reconfigurable Computing Devices. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_69
Download citation
DOI: https://doi.org/10.1007/3-540-46117-5_69
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-44108-3
Online ISBN: 978-3-540-46117-3
eBook Packages: Springer Book Archive