Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol

Abstract

In this paper, we report two of our recent efforts in applying formal verification methods to our real hardware designs. The first one is to try to verify ATM switch LSI chips through the combined use of a theorem prover and model checking programs, and the second one is to try to formally verify the correctness of a cache coherency protocol used in one of our parallel PC servers by model checking programs. In both cases, the verifications themselves were successful (we could really verify the “abstracted/simplified” designs). We could not, however, get much benefits from formal methods, since the verification process was not automatic but interactive. We had to spend significant amount of human time and human efforts in applying formal verification techniques, which made it very difficult to verify designs “in time”, that is, before the design process finishes. We review our experiences and describe problems that we typically encounter in application of formal verification techniques to real life designs.