Abstract
Field Programmable Gate Arrays (FPGAs) can provide the most suitable circuits for given problems by reconfiguring its circuits. In this paper, we show that a FPGA chip can achieve about 120 times of speedup compared with a workstation (Ultra-Sparc 200 MHz) in the computation of a co-evolution of strategies and scores in Iterated Prisoner’s Dilemma game. This speedup makes it possible to challenge more complex problems beyond the limitation by software.
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© 1999 Springer-Verlag Berlin Heidelberg
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Yamaguchi, Y., Maruyama, T., Hoshino, T. (1999). High Speed Hardware Computation of Co-evolution Models. In: Floreano, D., Nicoud, JD., Mondada, F. (eds) Advances in Artificial Life. ECAL 1999. Lecture Notes in Computer Science(), vol 1674. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48304-7_76
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DOI: https://doi.org/10.1007/3-540-48304-7_76
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-66452-9
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