Abstract
In this paper, we present an efficient fixed-size systolic array for Montgomery's modular multiplication. The array is designed by the LPGS (Locally Parallel Globally Sequential) partition method [14] and can perform efficiently modular multiplication for the input data with arbitrary bits. Also, we address a computation pipelining technique, which improves the throughput and minimizes the buffer size used. With the analysis of VHDL simulation, we discuss a gap between a theoretical optimal number of partition and an empirical one.
This work is supported by the Korea Telecom, KOREA under a grant NO. 98-13.
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Lee, SW., Kim, HS., Kim, JJ., Kim, TG., Yoo, KY. (1999). Efficient Fixed-Size Systolic Arrays for the Modular Multiplication. In: Asano, T., Imai, H., Lee, D.T., Nakano, Si., Tokuyama, T. (eds) Computing and Combinatorics. COCOON 1999. Lecture Notes in Computer Science, vol 1627. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48686-0_44
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DOI: https://doi.org/10.1007/3-540-48686-0_44
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