Skip to main content
SpringerLink
Log in
Book cover

International Conference on Formal Methods in Computer-Aided Design

FMCAD 1998: Formal Methods in Computer-Aided Design pp 204–221Cite as

A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool

  • Conference paper
  • First Online:

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1522))

Abstract

High-level synthesis tools generate rtl designs from algorithmic behavioral specifications and consist of well defined tasks. Widely used algorithms for these tasks retain the overall control flow structure of the behavioral specification allowing limited code motion. Further, hls algorithms are oblivious to the mathematical properties of arithmetic and logic operators, selecting and sharing rtl library modules solely based on matching uninterpreted function symbols and constants. This paper reports a Verification methodology that effectively exploits these features to achieve efficient and fully automated Verification of synthesized designs and its incorporation in a relatively mature hls tool.

In the proposed methodology, a correctness condition generator is tightly integrated with the hls tool to automatically generate (1) formal specifications of the behavior and the rtl design, (2) the correctness lemmas establishing equivalence between them, and (3) their proof scripts that can be submitted to a higher-order logic proof checker without further human interaction.

This work is sponsored in part by DARPA and monitored by US Army Ft. Huachuca under contract number DABT63-96-C-0051.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. G. De Micheli, “Synthesis and Optimization of Digital Circuits”, McGraw-Hill, 1994.

    Google Scholar 

  2. D.E. Thomas et al., “Algorithmic and Register Transfer Level Synthesis: The System Architect’s Workbench”, Kluwer Academic Publishers, 1990.

    Google Scholar 

  3. Srinivas Devadas, Hi-Keung Tony Ma, Richard Newton, “On Verification of Sequential Machines at Differing Levels of Abstraction”, IEEE Transactions on Computer-Aided Design, June 1988.

    Google Scholar 

  4. Michael McFarland, “An Abstract Model of Behavior for Hardware Descriptions”, IEEE Transactions on Computers, July 1983.

    Google Scholar 

  5. F. Corella, R. Camposano, R. Bergamaschi, M. Payer, “Verification of Synchronous Sequential Circuits Obtained from Algorithmic Specifications,” Proc. Intl. Workshop on Formal Methods in VLSI Design, Miami, 1991.

    Google Scholar 

  6. Reinaldo A. Bergamaschi, Salil Raje, “Observable Time Windows: Verifying The Results of High-Level Synthesis”, IEEE Design & Test of Computers”, May 1997.

    Google Scholar 

  7. Steven Johnson, “Synthesis of Digital Designs from Recursion Equations”, MIT Press, Cambridge, 1984.

    Google Scholar 

  8. Ranga Vemuri, “On the Notion of Normal Form Register-Level Structures and Its Applications in Design-Space Exploration”, European Design Automation Conference, March 1990.

    Google Scholar 

  9. F. Feldbusch, R. Kumar, “Verification of Synthesized Circuits at Register Transfer Level with Flow Graphs,” Proc. IEEE EDAC Conf., pp. 22–26, 1991.

    Google Scholar 

  10. Sreeranga Rajan, “Correctness Transformations in High Level Synthesis: Formal Verification”, Proceedings of the International Conference on Computer Hardware Description Languages, Japan, August 1995.

    Google Scholar 

  11. N. Shankar, S. Owre and J. M. Rushby, “The PVS Proof Checker: A Reference Manual (Beta Release)”, March 1993.

    Google Scholar 

  12. Dirk Eisnbiegler, Ramayya Kumar, “Formally Embedding Existing High Level Synthesis Algorithms”, “Correct Hardware Design and Verification Methods”, Germany, October 1995.

    Google Scholar 

  13. Luc Claesen, Mark Genoe, Eric Verlind, Frank Proesmans, Hugo De Man, “SFG-Tracing: A Methodology of Design for Verifiability”, Proceedings of Advanced Workshop on Correct Hardware Design Methodologies, North-Holland, 1991.

    Google Scholar 

  14. Luc Claesen, Frank Proesmans, Eric Verlind, Hugo De Man, “SFG-Tracing: A Methodology for the Automatic Verification of MOS Transistor Level Implementations from High-Level Behavioral Specifications”, Proc. Intl. Workshop on Formal Methods in VLSI Design, Miami, 1991.

    Google Scholar 

  15. Francisco Corella, “Automated High-Level Verification Against Clocked Algorithmic Specifications,” Proc. Computer Hardware Description Languages and Their Applications, April 1993.

    Google Scholar 

  16. Francisco Corella, “Automated Verification of Behavioral Equivalence for Microprocessors”, Research Report, IBM Research division, T.J. Watson Research Center, 1992.

    Google Scholar 

  17. Jerry R. Burch and David L. Dill, “Automatic Verification of Pipelined Microprocessor Control”, Proceedings of Computer-Aided Verification, July 1994.

    Google Scholar 

  18. M. K. Srivas and S. P. Miller, “Formal Verification of the AAMP5 Microprocessor,” Chapter 7 in Industrial Applications of Formal Verification.

    Google Scholar 

  19. A. Takach and W. Wolf, “Scheduling Constraint Generation for Communicating Processes”, Princeton University, November 1993.

    Google Scholar 

  20. D. E. Thomas, R. L. Blackburn, and J. V. Rajan, “Linking the Behavioral and Structural Domains of Representation for Digital System Design”, IEEE Trans. CAD, vol. CAD-6, pp. 103–110, January 1987.

    Google Scholar 

  21. F. J. Kurdahi, A. C. Parker, “REAL: A Program for REgister ALlocation”, Proceedings of the 24th ACM/IEEE Design Automation Conference, pp. 210–215, 1987.

    Google Scholar 

  22. S. Owre, N. Shankar, J. M. Rushby, “The PVS Specification Language (Beta Release)”, June 1993.

    Google Scholar 

  23. J. Roy, N. Kumar, R. Dutta, R. Vemuri, “DSS: A Distributed High-Level Synthesis System”, IEEE Design and Test of Computers, June 1992.

    Google Scholar 

  24. R. Dutta, J. Roy, R. Vemuri, “Distributed Design Space Exploration for High-Level Synthesis Systems”, 29th Design Automation Conference, pp. 644–650, 1992.

    Google Scholar 

  25. Sriram Govindarajan, Ranga Vemuri, “Dynamic Bounding of Successor Force Computations in the Force Directed List Scheduling Algorithm”, International Conference on Computer Design (ICCD), October 1997.

    Google Scholar 

  26. Sriram Govindarajan, Ranga Vemuri, Cone-Based Clustering Heuristic for List Scheduling Algorithms, Proceedings of the European Design and Test Conference, pp. 456–462., (ED&TC), March 1997.

    Google Scholar 

  27. Srinivas Katkoori, Jay Roy, Ranga Vemuri, “A Hierarchical Register Optimization Algorithm for Behavioral Synthesis”, Proceedings of International Conference on VLSI Design, pp. 126–134, Banglore, India 1996.

    Google Scholar 

  28. R. Vemuri et al, “Experiences in Functional Validation of a High Level Synthesis System”, 30th ACM/IEEE Design Automation Conference, 1993.

    Google Scholar 

  29. E.M. Clarke, E.A. Emerson, A.P. Sistla, “Automatic Verification of Finite-State Concurrent Systems using Temporal Logic Specifications”, ACM Trans. Prog. Lang. Syst., pp. 244–263, 1986.

    Google Scholar 

  30. N. Narasimhan, R. Vemuri, “Specification of Control Flow Properties for Verification of Synthesized VHDL Designs”, “Proceedings of Formal Methods in CAD”, pp. 327–345, Springer-Verlag, November 1996.

    Google Scholar 

  31. Kenneth L. McMillan, “Symbolic Model Checking: An Approach to the State Explosion Problem” Carnegie Mellon University, 1992.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Digital Design Environments Laboratory ECECS Department, University of Cincinnati, Cincinnati, Ohio, 45221-0030, USA

    Nazanin Mansouri & Ranga Vemuri

Authors
  1. Nazanin Mansouri
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Ranga Vemuri
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Department of Computer Science, University of Utah, 50 S Central Campus, Salt Lake City, UT, 841112-9205, USA

    Ganesh Gopalakrishnan

  2. Department of Computer Science, Brigham Young University, 3361 TMCB, Provo, UT, 84602-6576, USA

    Phillip Windley

Rights and permissions

Reprints and permissions

Copyright information

© 1998 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Mansouri, N., Vemuri, R. (1998). A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool. In: Gopalakrishnan, G., Windley, P. (eds) Formal Methods in Computer-Aided Design. FMCAD 1998. Lecture Notes in Computer Science, vol 1522. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-49519-3_15

Download citation

  • DOI: https://doi.org/10.1007/3-540-49519-3_15

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-65191-8

  • Online ISBN: 978-3-540-49519-2

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation