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Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study

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Book cover Formal Methods in Computer-Aided Design (FMCAD 1998)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1522))

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Abstract

There is a large class of circuits (including pipeline and out-of-order execution components) which can be formally verified while completely ignoring the precise characteristics (e.g. word-size) of the data manipulated by the circuits. In the literature, this is often described as the use of uninterpreted functions, implying that the concrete operations applied to the data are abstracted into unknown and featureless functions. In this paper, we briefly introduce an abstract unifying model for such datainsensitive circuits, and claim that the development of such models, perhaps even a theory of circuit schemas, can significantly contribute to the development of efficient and comprehensive verification algorithms combining deductive as well as enumerative methods.

As a case study, we present in this paper an algorithm for out-of-order execution with in-order retirement and show it to be a refinement of the sequential instruction execution algorithm. Refinement is established by deductively proving (using pvs) that the register files of the out-of-order algorithm and the sequential algorithm agree at all times if the two systems are synchronized at instruction retirement time.

This research was supported in part by a gift from Intel, a grant from the Minerva foundation, and an Infrastructure grant from the Israeli Ministry of Science.

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Author information

Authors and Affiliations

  1. Weizmann Institute of Science, Rehovot, Israel

    Amir Pnueli & T. Arons

Authors
  1. Amir Pnueli
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  2. T. Arons
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Editor information

Editors and Affiliations

  1. Department of Computer Science, University of Utah, 50 S Central Campus, Salt Lake City, UT, 841112-9205, USA

    Ganesh Gopalakrishnan

  2. Department of Computer Science, Brigham Young University, 3361 TMCB, Provo, UT, 84602-6576, USA

    Phillip Windley

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© 1998 Springer-Verlag Berlin Heidelberg

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Pnueli, A., Arons, T. (1998). Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study. In: Gopalakrishnan, G., Windley, P. (eds) Formal Methods in Computer-Aided Design. FMCAD 1998. Lecture Notes in Computer Science, vol 1522. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-49519-3_23

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  • DOI: https://doi.org/10.1007/3-540-49519-3_23

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  • Print ISBN: 978-3-540-65191-8

  • Online ISBN: 978-3-540-49519-2

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