Abstract
Since the sorting is one of the most fundamental and frequently used operation in the current computer system, we have so far developed a high speed hardware sorter.
In this paper, we present the results of the performance evaluation of the 18-stage pipeline hardware sorter. One of the key features of our sorter is its employment of novel "string length tuning" algorithm, by which any length of records can be sorted very efficiently. The sorter can sort 256K records at one time. The sorting speed is 4 Mbytes/sec. Its memory capacity is 8 Mbytes. This practical scale sorting machine is connected to the system bus of a host computer through the bus adapter. Incorporating the sorter as a device in the operating system, we have evaluated its performance. The sorter showed much higher performance than the software sort utility on the host machine.
We are now making a sorting element board into a VLSI sort chip. The future plan is also briefly presented.
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© 1989 Springer-Verlag Berlin Heidelberg
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Kitsuregawa, M., Yang, W., Fushimi, S. (1989). Evaluation of 18-stage pipeline hardware sorter. In: Boral, H., Faudemay, P. (eds) Database Machines. IWDM 1989. Lecture Notes in Computer Science, vol 368. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-51324-8_33
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DOI: https://doi.org/10.1007/3-540-51324-8_33
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