Abstract
The paper deals with the analysis of bit-level systolic arrays for digital contour smoothing. Procedures for obtaining new bit-level systolic arrays, which improve the already known designs, were suggested. New systolic arrays proposed on the bit level have a simple structure. They consist of single type cells (1-bit full adders), which are separated by 1-bit delay elements. They are suitable for the VLSI implementation.
This work was done during author's working stay in the International Basis Laboratory of Image Processing and Computer Graphics in Berlin in October and November 1988.
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7. References
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Glasa, J. (1989). Bit-level systolic arrays for digital contour smoothing. In: Cantoni, V., Creutzburg, R., Levialdi, S., Wolf, G. (eds) Recent Issues in Pattern Analysis and Recognition. Lecture Notes in Computer Science, vol 399. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-51815-0_47
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DOI: https://doi.org/10.1007/3-540-51815-0_47
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