Abstract
An interconnection network for a high-performance parallel computer for database, Lisp and Prolog applications is currently being developed. To meet the requirements derived from applications a multistage interconnection network is chosen. The selection of the switching elements and their optimization was done by simulation with randomly distributed load patterns as well as with traces from applications. The proposed network is composed of 8 × 8 crossbar switches with four independent packet buffers per input port. Each switch will be contained in a single VLSI-chip. The network will operate with a bandwidth of 20 Mbytes/sec on each communication channel.
This is a preview of subscription content, log in via an institution.
Preview
Unable to display preview. Download preview PDF.
7. References
Hutner F., ”Evaluation of Alternative Switch Types for a Delta Network”, Siemens internal report No. SYS 3-BeG009/89 (in german)
Reyzl E., Eckardt H., ”Performance Evaluation For High-Performance Interconnection Networks”, Proc. of ”ITG/GI-Fachtagung Architektur von Rechensystemen”, Munich, 1990, VDE-Verlag, Düsseldorf
Siegel H.J., ”Interconnection Networks for Large-Scale Parallel Processing”, Lexington Books, Lexington, 1986
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1990 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Holzner, R., Tomann, S. (1990). Design and simulation of a multistage interconnection network. In: Burkhart, H. (eds) CONPAR 90 — VAPP IV. VAPP CONPAR 1990 1990. Lecture Notes in Computer Science, vol 457. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-53065-7_117
Download citation
DOI: https://doi.org/10.1007/3-540-53065-7_117
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-53065-7
Online ISBN: 978-3-540-46597-3
eBook Packages: Springer Book Archive