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A hierarchical approach to hardware design

  • Part III Parallel Architectures And VLSI Logic
  • Conference paper
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Concurrency: Theory, Language, and Architecture (CONCURRENCY 1989)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 491))

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Abstract

It is proposed that hierarchical hardware development can benefit from techniques inspired by the hierarchical development of software, and that claim is supported with an example.

A series of levels of abstraction are indicated, the most interesting of which deal with timing of device observables, and criteria are given for moving between them. One of the techniques considered, temporal decoding, enables an event to be refined by a sequence of smaller events. Use of the hierarchy is sketched for a stack array of Mead and Conway.

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Akinori Yonezawa Takayasu Ito

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© 1991 Springer-Verlag Berlin Heidelberg

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Sanders, J.W. (1991). A hierarchical approach to hardware design. In: Yonezawa, A., Ito, T. (eds) Concurrency: Theory, Language, and Architecture. CONCURRENCY 1989. Lecture Notes in Computer Science, vol 491. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-53932-8_56

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  • DOI: https://doi.org/10.1007/3-540-53932-8_56

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-53932-2

  • Online ISBN: 978-3-540-46452-5

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