Abstract
Image processing generally requires to manipulate a large number of data of small granularity. In this paper a multiprocessor architecture which allows an efficient image processing in VLSI is proposed. The proposed network is as efficient as hypercube using O(n 1/2 log n) less chip area when n is the number of nodes in the network. The effectiveness of the proposed design is verified by studying some important image processing algorithms developed for hypercube network. The proposed architecture is also simple and modular, and thus it is relatively easier to develop efficient fault tolerance designs.
This work was supported in part by NSF Grant MIP-9009643.
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© 1991 Springer-Verlag Berlin Heidelberg
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Youn, H.Y. (1991). An efficient multiprocessor architecture for image processing in VLSI. In: Dehne, F., Fiala, F., Koczkodaj, W.W. (eds) Advances in Computing and Information — ICCI '91. ICCI 1991. Lecture Notes in Computer Science, vol 497. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-54029-6_199
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DOI: https://doi.org/10.1007/3-540-54029-6_199
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