Abstract
This paper concerns the computational aspects of the reconfigurable network model. The computational power of the model is investigated under several network topologies and assuming several variants of the model. In particular, it is shown that there are reconfigurable machines based on simple network topologies, that are capable of solving large classes of problems in constant time. These classes depend on the kinds of switches assumed for the network nodes. Reconfigurable networks are also compared with various other models of parallel computation, like PRAM's and Branching Programs.
Supported in part by an Allon Fellowship, by a Bantrell Fellowship and by a Walter and Elise Haas Career Development Award.
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References
D. Barrington, Bounded-Width Polynomial-Size Branching Programs Recognize Exactly Those Languages in NC1, Proc. 18th ACM Symp. on Theory of Computing, 1986, pp. 1–5.
P. Beame, Limits on the Power of Concurrent-Write Parallel Machines, Proc. 18th ACM Symp. on Theory of Computing, 1986, pp. 169–176.
P. Beame and J. Hastad, Optimal Bounds for Decision Problems on the CRCW PRAM, Proc. 19th ACM Symp. on Theory of Computing, 1987, pp. 83–93.
A. Bar-Noy and D. Peleg, Square Meshes are not Always Optimal, IEEE Trans. on Computers 40, (1991), 196–204.
A. Ben-Asher, D. Peleg, R. Ramaswami and A. Schuster, The Power of Reconfiguration, J. of Parallel and Distributed Computing, Special Issue on the Frontiers of Massively Parallel Computation, to appear 1991.
A. Ben-Asher and A. Schuster, Optical Splitting Graphs, The 1990 Int. Topical Meeting on Optical Computing, Kobe, Japan, April 1990.
A. Ben-Asher and A. Schuster, Algorithms and Optical Implementation for Reconfigurable Networks, Proc. 5th Jerusalem Conf. on Information Technology, 1990, 225–235.
A. Ben-Asher and A. Schuster, Reconfigurable Paths and Bus Usage, Hebrew University Technical Report #90-14, January 1990.
R. Cleve, Toward Optimal Simulations of Formulas by Bounded-Width Programs, Proc. 22nd ACM Symp. on Theory of Computing, May 1990, pp. 271–277.
J. Cai and R.J. Lipton, Subquadratic Simulations of Circuits by Branching Programs, Proc. 30th IEEE Symp. on Foundation of Computer Sci., 1989, pp. 568–573.
J.P. Gray and T.A. Kean, Configurable Hardware: A New Paradigm for Computation, Proc. 10th Caltech conf. on VLSI, March 1989, pp. 279–295.
F.T. Leighton, Tight Bounds on the Complexity of Parallel Sorting, Proc. 16th Symp. on Theory of Computing, 1984, pp.71–80.
H. Li and M. Maresca, Polymorphic-torus architecture for computer vision, IEEE Trans. Pattern Anal. Machine Intell., Vol. 11, No. 3, pp. 233–243, March 1989.
H. Li and M. Maresca, Polymorphic-torus network, IEEE Trans. Comput., Vol. 38, No. 9, pp. 1345–1351, September 1989.
O. Menzilcioglu, H. T. Kung and S. W. Song, Comprehensive Evaluation of a Two-dimensional Configurable Array, Proc. 19th Symp. on Fault-Tolerant Computing, Chicago, Illinois, June 1989, pp. 93–100.
R. Miller, V.K. Prasanna-Kumar, D.I. Reisis and Q.F. Stout, Data Movement Operations and Applications on Reconfigurable VLSI Arrays, proc. 1988 Intl. Conf. on Parallel Processing, Vol. I, 205–208.
J.M. Moshell and J. Rothstein, Bus Automata and Immediate Languages, Information and Control 40, (1979), 88–121.
T. Nakatani, Interconnections by Superposed Parallel Busses, Ph.D. dissertation, Princeton, 1987.
D. Reisis and V.K. Prasanna-Kumar, VLSI Arrays with Reconfigurable Busses, Proc. 1st Intl. Conf. on SuperComputing, 1987, pp. 732–742.
L. Snyder, Introduction to the configurable highly parallel computer, Computer 15, (1982), 47–56.
Q. F. Stout, Mesh-Connected Computers with Broadcasting, IEEE Trans. on Computers, c-32, (1983), 826–830.
X. Thibault, D. Comte and P. Siron, A Reconfigurable Optical Interconnection Network for Highly Parallel Architecture, Proc. 2nd Symp. on the Frontiers of Massively Parallel Computation, 1989.
C.D. Thompson, The VLSI Complexity of Sorting, IEEE Trans. Comput. 32, (1983), 1171–1184.
B. Wang and G. Chen, Constant Time Algorithms for the Transitive Closure and Some Related Graph Problems on Processor Arrays with Reconfigurable Bus Systems, IEEE Transactions on Parallel and Distributed Systems, Vol. 1, No. 4, October 1990.
B. Wang, G. Chen and F. Lin, Constant Time Sorting on a Processor Array with a Reconfigurable Bus-System, Information Processing Letters 34, (1990), pp. 187–192.
I. Wegener, The Complexity of Boolean functions, John Wiley, 1988.
Xilinx Inc., The programmable Gate Array Design Handbook, San Jose, Calif., 1986.
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© 1991 Springer-Verlag Berlin Heidelberg
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Ben-Asher, Y., Peleg, D., Ramaswami, R., Schuster, A. (1991). The power of reconfiguration. In: Albert, J.L., Monien, B., Artalejo, M.R. (eds) Automata, Languages and Programming. ICALP 1991. Lecture Notes in Computer Science, vol 510. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-54233-7_130
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DOI: https://doi.org/10.1007/3-540-54233-7_130
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