Generating memory-efficient imperative data structures from systolic programs

Abstract

The concept of systolic arrays is mainly used to design highly regular VLSI circuits. However, it can be also used as a source to generate regular imperative programs for existing non-systolic distributed-memory parallel architectures. In this paper, we present a low complexity technique for generating and optimizing data structures for the output program. We also propose several source-to-source transformations of input programs which further improve the efficiency of the optimization process.